Re: [PATCH] clk: qcom: regmap-phy-mux: Rework the implementation

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 6/11/26 9:38 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 08, 2026 at 10:09:55AM -0500, Bjorn Andersson wrote:
>>
>> On Thu, 09 Apr 2026 13:57:45 +0200, Konrad Dybcio wrote:
>>> The sole reason this hw exists is to let the branch clock downstream of
>>> it keep running, with the PHY disengaged. This is not possible with the
>>> current implementation, as the enabled status is hijacked to mean
>>> "enabled" = "use fast/PHY source" and "disabled" = "use XO source".
>>>
>>> This is an issue, since the mux enable state follows that of the child
>>> branch, making the desired "child enabled, MUX @ XO" combination
>>> impossible.
>>>
>>> [...]
>>
>> Applied, thanks!
>>
>> [1/1] clk: qcom: regmap-phy-mux: Rework the implementation
>>       commit: e108373c54fbc844b7f541c6fd7ecb31772afd3c
> 
> This breaks at PCIe at least on SM8350. The attached WiFi card is
> not detected anymore. Rewerting the patch makes it work again.

Hm, that's anticlimactic. Can you please dump:

gcc_pcie_0_pipe_clk_src: gcc+0x6b054
gcc_pcie_0_pipe_clk: gcc+0x52008

gcc_pcie_1_pipe_clk_src: gcc+0x8d054
gcc_pcie_1_pipe_clk: gcc+0x52000

Konrad