[PATCH] mtd: spi-nor: Describe locking support for MX25L51245G

[PATCH] mtd: spi-nor: Describe locking support for MX25L51245G

[Marek Vasut]

The MX25L51245G part has the same 4-BP locking mechanism as MX25L12805D.
Describe the locking support.

Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Cheng Ming Lin <chengminglin@mxic.com.tw>
Cc: Michael Walle <mwalle@kernel.org>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Pratyush Yadav <pratyush@kernel.org>
Cc: Richard Weinberger <richard@nod.at>
Cc: Takahiro Kuwano <takahiro.kuwano@infineon.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mtd@lists.infradead.org
---
 drivers/mtd/spi-nor/macronix.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index b3fdb4b2fa1ca..4de1b490b16b6 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -165,6 +165,7 @@ static const struct flash_info macronix_nor_parts[] = {
 	}, {
 		/* MX25L51245G, MX25L51273G, MX66L51235F */
 		.id = SNOR_ID(0xc2, 0x20, 0x1a),
+		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,
 	}, {
 		/* MX66L1G45G */
 		.id = SNOR_ID(0xc2, 0x20, 0x1b),
-- 
2.53.0

RE: [PATCH] mtd: spi-nor: Describe locking support for MX25L51245G

[Takahiro.Kuwano]

Hi Marek,

> The MX25L51245G part has the same 4-BP locking mechanism as MX25L12805D.
> Describe the locking support.
> 
> Signed-off-by: Marek Vasut <marex@nabladev.com>
> ---
> Cc: Cheng Ming Lin <chengminglin@mxic.com.tw>
> Cc: Michael Walle <mwalle@kernel.org>
> Cc: Miquel Raynal <miquel.raynal@bootlin.com>
> Cc: Pratyush Yadav <pratyush@kernel.org>
> Cc: Richard Weinberger <richard@nod.at>
> Cc: Takahiro Kuwano <takahiro.kuwano@infineon.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-mtd@lists.infradead.org
> ---

Can you test locking as described in [1] and provide test log?

>  drivers/mtd/spi-nor/macronix.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index b3fdb4b2fa1ca..4de1b490b16b6 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -165,6 +165,7 @@ static const struct flash_info macronix_nor_parts[] = {
>         }, {
>                 /* MX25L51245G, MX25L51273G, MX66L51235F */
>                 .id = SNOR_ID(0xc2, 0x20, 0x1a),
> +               .flags = SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP,

According to datasheets [2][3][4], those chips have TB bit in Configuration
Register bit-3 and the bit is OTP. The existing HAS_TB and HAS_TB_SR_BIT6
flags don't work as they expect non-OTP bit in Status Register.
Just supporting top area protection (TB==0) would be fine with me, but in
that case, fixup should check TB and activate locking only when TB==0.

Thanks,
Takahiro

>         }, {
>                 /* MX66L1G45G */
>                 .id = SNOR_ID(0xc2, 0x20, 0x1b),
> --
> 2.53.0

[1] https://docs.kernel.org/driver-api/mtd/spi-nor.html
[2] https://www.macronix.com/Lists/Datasheet/Attachments/8381/MX25L51245G,%203V,%20512Mb,%20v1.3.pdf
[3] https://www.mxic.com.tw/Lists/Datasheet/Attachments/9176/MX25L51273G,%203V,%20512Mb,%20v1.7.pdf
[4] https://www.macronix.com/Lists/Datasheet/Attachments/8657/MX66L51235F,%203V,%20512Mb,%20v1.1.pdf