[PATCH V1 RESEND] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[PATCH V1 RESEND] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[Sangwook Shin]

From: Kyunghwan Seo <khwan.seo@samsung.com>

Fix the PMU register bits for the ExynosAutoV920 SoC.
This SoC has different bit information compared to its previous
version, ExynosAutoV9, and we have made the necessary adjustments.

rst_stat_bit:
    - ExynosAutoV920 cl0 : 0
    - ExynosAutoV920 cl1 : 1

cnt_en_bit:
    - ExynosAutoV920 cl0 : 8
    - ExynosAutoV920 cl1 : 8

Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
---
 drivers/watchdog/s3c2410_wdt.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 30450e99e5e9..bdd81d8074b2 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -72,6 +72,8 @@
 #define EXYNOS850_CLUSTER1_WDTRESET_BIT		23
 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT	25
 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT	24
+#define EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT	0
+#define EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT	1
 
 #define GS_CLUSTER0_NONCPU_OUT			0x1220
 #define GS_CLUSTER1_NONCPU_OUT			0x1420
@@ -312,9 +314,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
 	.mask_bit = 2,
 	.mask_reset_inv = true,
 	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
-	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
+	.rst_stat_bit = EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT,
 	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
-	.cnt_en_bit = 7,
+	.cnt_en_bit = 8,
 	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
 		  QUIRK_HAS_DBGACK_BIT,
@@ -325,9 +327,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
 	.mask_bit = 2,
 	.mask_reset_inv = true,
 	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
-	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
+	.rst_stat_bit = EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT,
 	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
-	.cnt_en_bit = 7,
+	.cnt_en_bit = 8,
 	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
 		  QUIRK_HAS_DBGACK_BIT,
-- 
2.40.1

Re: [PATCH V1 RESEND] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[Krzysztof Kozlowski]

On 26/02/2025 08:21, Sangwook Shin wrote:
> From: Kyunghwan Seo <khwan.seo@samsung.com>
> 
> Fix the PMU register bits for the ExynosAutoV920 SoC.
> This SoC has different bit information compared to its previous
> version, ExynosAutoV9, and we have made the necessary adjustments.
> 
> rst_stat_bit:
>     - ExynosAutoV920 cl0 : 0
>     - ExynosAutoV920 cl1 : 1
> 
> cnt_en_bit:
>     - ExynosAutoV920 cl0 : 8
>     - ExynosAutoV920 cl1 : 8
> 
> Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
> Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>

Resending while ignoring all previous emails, so we should do the work
twice. If you ever wonder why your patches are not applied, you got answer.


<form letter>
This is a friendly reminder during the review process.

It looks like you received a tag and forgot to add it.

If you do not know the process, here is a short explanation:
Please add Acked-by/Reviewed-by/Tested-by tags when posting new versions
of patchset, under or above your Signed-off-by tag, unless patch changed
significantly (e.g. new properties added to the DT bindings). Tag is
"received", when provided in a message replied to you on the mailing
list. Tools like b4 can help here. However, there's no need to repost
patches *only* to add the tags. The upstream maintainer will do that for
tags received on the version they apply.

Please read:
https://elixir.bootlin.com/linux/v6.12-rc3/source/Documentation/process/submitting-patches.rst#L577

If a tag was not added on purpose, please state why and what changed.
</form letter>


Best regards,
Krzysztof

[PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[Sangwook Shin]

From: Kyunghwan Seo <khwan.seo@samsung.com>

Fix the PMU register bits for the ExynosAutoV920 SoC.
This SoC has different bit information compared to its previous
version, ExynosAutoV9, and we have made the necessary adjustments.

rst_stat_bit:
    - ExynosAutoV920 cl0 : 0
    - ExynosAutoV920 cl1 : 1

cnt_en_bit:
    - ExynosAutoV920 cl0 : 8
    - ExynosAutoV920 cl1 : 8

Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
---
v1 -> v2: Restore previous email history and tags.

 drivers/watchdog/s3c2410_wdt.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 30450e99e5e9..bdd81d8074b2 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -72,6 +72,8 @@
 #define EXYNOS850_CLUSTER1_WDTRESET_BIT		23
 #define EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT	25
 #define EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT	24
+#define EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT	0
+#define EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT	1
 
 #define GS_CLUSTER0_NONCPU_OUT			0x1220
 #define GS_CLUSTER1_NONCPU_OUT			0x1420
@@ -312,9 +314,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
 	.mask_bit = 2,
 	.mask_reset_inv = true,
 	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
-	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
+	.rst_stat_bit = EXYNOSAUTOV920_CLUSTER0_WDTRESET_BIT,
 	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
-	.cnt_en_bit = 7,
+	.cnt_en_bit = 8,
 	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
 		  QUIRK_HAS_DBGACK_BIT,
@@ -325,9 +327,9 @@ static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
 	.mask_bit = 2,
 	.mask_reset_inv = true,
 	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
-	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
+	.rst_stat_bit = EXYNOSAUTOV920_CLUSTER1_WDTRESET_BIT,
 	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
-	.cnt_en_bit = 7,
+	.cnt_en_bit = 8,
 	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
 		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
 		  QUIRK_HAS_DBGACK_BIT,
-- 
2.40.1

Re: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[Krzysztof Kozlowski]

On 18/03/2025 01:44, Sangwook Shin wrote:
> From: Kyunghwan Seo <khwan.seo@samsung.com>
> 
> Fix the PMU register bits for the ExynosAutoV920 SoC.
> This SoC has different bit information compared to its previous
> version, ExynosAutoV9, and we have made the necessary adjustments.
> 
> rst_stat_bit:
>     - ExynosAutoV920 cl0 : 0
>     - ExynosAutoV920 cl1 : 1
> 
> cnt_en_bit:
>     - ExynosAutoV920 cl0 : 8
>     - ExynosAutoV920 cl1 : 8
> 
> Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
> ---
> v1 -> v2: Restore previous email history and tags.
> 

Why do you send patches which were applied?

Best regards,
Krzysztof

RE: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[sw617.shin]

Hello, Krzysztof

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, March 18, 2025 4:20 PM
> To: Sangwook Shin <sw617.shin@samsung.com>; alim.akhtar@samsung.com;
> wim@linux-watchdog.org; linux@roeck-us.net
> Cc: linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> kernel@vger.kernel.org; Kyunghwan Seo <khwan.seo@samsung.com>
> Subject: Re: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for
> ExynosAutoV920 SoC
> 
> On 18/03/2025 01:44, Sangwook Shin wrote:
> > From: Kyunghwan Seo <khwan.seo@samsung.com>
> >
> > Fix the PMU register bits for the ExynosAutoV920 SoC.
> > This SoC has different bit information compared to its previous
> > version, ExynosAutoV9, and we have made the necessary adjustments.
> >
> > rst_stat_bit:
> >     - ExynosAutoV920 cl0 : 0
> >     - ExynosAutoV920 cl1 : 1
> >
> > cnt_en_bit:
> >     - ExynosAutoV920 cl0 : 8
> >     - ExynosAutoV920 cl1 : 8
> >
> > Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
> > Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> > Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> > Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
> > ---
> > v1 -> v2: Restore previous email history and tags.
> >
> 
> Why do you send patches which were applied?
> 
> Best regards,
> Krzysztof

I can't see this patch in -next yet.
Could you please advise me where it is? Then, I will check again.
If there are any missing parts that I need to handle on my end,
please let me know.

Re: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[Krzysztof Kozlowski]

On 18/03/2025 09:37, sw617.shin@samsung.com wrote:
>> Why do you send patches which were applied?
>>
>> Best regards,
>> Krzysztof
> 
> I can't see this patch in -next yet.
> Could you please advise me where it is? Then, I will check again.
> If there are any missing parts that I need to handle on my end,
> please let me know.
I don't think you tried enough.

Best regards,
Krzysztof

RE: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[sw617.shin]

Hello Krzysztof

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Tuesday, March 18, 2025 5:57 PM
> To: sw617.shin@samsung.com; alim.akhtar@samsung.com; wim@linux-
> watchdog.org; linux@roeck-us.net
> Cc: linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> kernel@vger.kernel.org; 'Kyunghwan Seo' <khwan.seo@samsung.com>
> Subject: Re: [PATCH v2] watchdog: s3c2410_wdt: Fix PMU register bits for
> ExynosAutoV920 SoC
> 
> On 18/03/2025 09:37, sw617.shin@samsung.com wrote:
> >> Why do you send patches which were applied?
> >>
> >> Best regards,
> >> Krzysztof
> >
> > I can't see this patch in -next yet.
> > Could you please advise me where it is? Then, I will check again.
> > If there are any missing parts that I need to handle on my end, please
> > let me know.
> I don't think you tried enough.
> 
> Best regards,
> Krzysztof

You're definitely right.
I found it with my colleague's help.
I was monitoring wrong ones.
Thanks for notice and sorry for making you uncomfortable.
Thank you.

[PATCH V1 RESEND] watchdog: s3c2410_wdt: Fix PMU register bits for ExynosAutoV920 SoC

[sw617.shin]

This is a friendly reminder for this patch.

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Thursday, February 13, 2025 1:56 PM
> To: 'Sangwook Shin' <sw617.shin@samsung.com>; krzk@kernel.org; wim@linux-
> watchdog.org; linux@roeck-us.net
> Cc: linux-arm-kernel@lists.infradead.org; linux-samsung-
> soc@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> kernel@vger.kernel.org; 'Kyunghwan Seo' <khwan.seo@samsung.com>
> Subject: RE: [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for
> ExynosAutoV920 SoC
> 
> Hello Sangwook
> 
> > -----Original Message-----
> > From: Sangwook Shin <sw617.shin@samsung.com>
> > Sent: Thursday, February 13, 2025 6:11 AM
> > To: krzk@kernel.org; alim.akhtar@samsung.com; wim@linux-watchdog.org;
> > linux@roeck-us.net
> > Cc: linux-arm-kernel@lists.infradead.org; linux-samsung-
> > soc@vger.kernel.org; linux-watchdog@vger.kernel.org; linux-
> > kernel@vger.kernel.org; Kyunghwan Seo <khwan.seo@samsung.com>;
> > Sangwook Shin <sw617.shin@samsung.com>
> > Subject: [PATCH] watchdog: s3c2410_wdt: Fix PMU register bits for
> > ExynosAutoV920 SoC
> >
> > From: Kyunghwan Seo <khwan.seo@samsung.com>
> >
> > Fix the PMU register bits for the ExynosAutoV920 SoC.
> > This SoC has different bit information compared to its previous
> > version, ExynosAutoV9, and we have made the necessary adjustments.
> >
> > rst_stat_bit:
> >     - ExynosAutoV920 cl0 : 0
> >     - ExynosAutoV920 cl1 : 1
> >
> > cnt_en_bit:
> >     - ExynosAutoV920 cl0 : 8
> >     - ExynosAutoV920 cl1 : 8
> >
> > Signed-off-by: Kyunghwan Seo <khwan.seo@samsung.com>
> > Signed-off-by: Sangwook Shin <sw617.shin@samsung.com>
> > ---
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> 
>