From: Mikko Perttunen <mperttunen@nvidia.com>
To: Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
linux-clk@vger.kernel.org
Cc: Svyatoslav Ryhel <clamor95@gmail.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Patrick Fischer <admin@tsv-stahl-riesa.de>,
admin@tsv-stahl-riesa.de
Subject: Re: [PATCH 2/3] soc/tegra: fuse: Store Tegra114 CPU and SoC speedo values
Date: Mon, 02 Nov 2026 16:47:13 +0900 [thread overview]
Message-ID: <9hOyUQJpQg-PaQkToACCxw@nvidia.com> (raw)
In-Reply-To: <20261029-upstream-speedo-t114-v1-2-81457cc9d94c@tsv-stahl-riesa.de>
On Thursday, October 29, 2026 6:33 PM Patrick Fischer via B4 Relay wrote:
> From: Patrick Fischer <admin@tsv-stahl-riesa.de>
>
> The Tegra114 CPU DFLL computes its OPP voltages from the CVB tables
> added in commit 5aba939e80f4 ("clk: tegra: dfll: Add CVB tables for
> Tegra114"), using tegra_sku_info.cpu_speedo_value. The Tegra114 speedo
> code computes this value but never stores it, so the DFLL uses speedo
> 0 and only the c0 coefficient remains. For CPU speedo IDs 1 to 3 c0 is
> 2190643 to 3395401, so "mv * 1000" in round_cvb_voltage() overflows and
> the OPP voltages are wrong.
>
> This is currently hidden by a zero voltage step with Palmas regulators,
> fixed in the next patch. With both fixes the CPU OPPs range from 1000 mV
> to 1270 mV on a device with CPU speedo 1742, which matches the vendor
> kernel.
>
> Store the SoC speedo value as well, as Tegra124 and Tegra210 do.
>
> Fixes: 5aba939e80f4 ("clk: tegra: dfll: Add CVB tables for Tegra114")
> Cc: stable@vger.kernel.org
> Signed-off-by: Patrick Fischer <admin@tsv-stahl-riesa.de>
> ---
> drivers/soc/tegra/fuse/speedo-tegra114.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/soc/tegra/fuse/speedo-tegra114.c b/drivers/soc/tegra/fuse/speedo-tegra114.c
> index 1e6c2b5be759..8bf1a1b1287a 100644
> --- a/drivers/soc/tegra/fuse/speedo-tegra114.c
> +++ b/drivers/soc/tegra/fuse/speedo-tegra114.c
> @@ -92,6 +92,9 @@ void __init tegra114_init_speedo_data(struct tegra_sku_info *sku_info)
> cpu_speedo_val = tegra_fuse_read_early(FUSE_CPU_SPEEDO_1) + 1024;
> soc_speedo_val = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0);
>
> + sku_info->cpu_speedo_value = cpu_speedo_val;
> + sku_info->soc_speedo_value = soc_speedo_val;
> +
> for (i = 0; i < CPU_PROCESS_CORNERS; i++)
> if (cpu_speedo_val < cpu_process_speedos[threshold][i])
> break;
>
> --
> 2.56.0
>
>
>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com> # Dalmore
next prev parent reply other threads:[~2026-11-02 7:47 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 9:32 [PATCH 0/3] Tegra114: Fix CPU DFLL voltages Patrick Fischer via B4 Relay
2026-10-29 9:32 ` [PATCH 1/3] soc/tegra: fuse: Fix Tegra114 speedo fuse offsets Patrick Fischer via B4 Relay
2026-10-29 10:11 ` Svyatoslav Ryhel
2026-11-02 7:41 ` Mikko Perttunen
2026-10-29 9:33 ` [PATCH 2/3] soc/tegra: fuse: Store Tegra114 CPU and SoC speedo values Patrick Fischer via B4 Relay
2026-10-29 10:11 ` Svyatoslav Ryhel
2026-11-02 7:47 ` Mikko Perttunen [this message]
2026-10-29 9:33 ` [PATCH 3/3] clk: tegra: dfll: Get the voltage step of range-based regulators Patrick Fischer via B4 Relay
2026-10-29 10:15 ` Svyatoslav Ryhel
2026-11-02 8:30 ` Mikko Perttunen
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