* [PATCH 0/3] LoongArch: KVM: Some tiny code cleanup
@ 2025-02-07 3:26 Bibo Mao
2025-02-07 3:26 ` [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection Bibo Mao
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Bibo Mao @ 2025-02-07 3:26 UTC (permalink / raw)
To: Tianrui Zhao; +Cc: Huacai Chen, WANG Xuerui, kvm, loongarch, linux-kernel
There is some tiny code cleanup with VM context switch or vCPU context
switch path. And add comments for feature macro so that it is easy to
understand.
Bibo Mao (3):
LoongArch: KVM: Fix typo issue about GCFG feature detection
LoongArch: KVM: Remove duplicated cache attribute setting
LoongArch: KVM: Set host with kernel mode when switch to VM mode
arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++
arch/loongarch/kvm/main.c | 4 ++--
arch/loongarch/kvm/switch.S | 2 +-
arch/loongarch/kvm/vcpu.c | 3 ---
4 files changed, 29 insertions(+), 6 deletions(-)
base-commit: 5c8c229261f14159b54b9a32f12e5fa89d88b905
--
2.39.3
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection 2025-02-07 3:26 [PATCH 0/3] LoongArch: KVM: Some tiny code cleanup Bibo Mao @ 2025-02-07 3:26 ` Bibo Mao 2025-02-09 9:38 ` Huacai Chen 2025-02-07 3:26 ` [PATCH 2/3] LoongArch: KVM: Remove duplicated cache attribute setting Bibo Mao 2025-02-07 3:26 ` [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode Bibo Mao 2 siblings, 1 reply; 10+ messages in thread From: Bibo Mao @ 2025-02-07 3:26 UTC (permalink / raw) To: Tianrui Zhao; +Cc: Huacai Chen, WANG Xuerui, kvm, loongarch, linux-kernel This is typo issue about GCFG feature macro, comments is added for these macro and typo issue is fixed here. Signed-off-by: Bibo Mao <maobibo@loongson.cn> --- arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++ arch/loongarch/kvm/main.c | 4 ++-- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h index 52651aa0e583..1a65b5a7d54a 100644 --- a/arch/loongarch/include/asm/loongarch.h +++ b/arch/loongarch/include/asm/loongarch.h @@ -502,49 +502,75 @@ #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ #define CSR_GCFG_GPERF_SHIFT 24 #define CSR_GCFG_GPERF_WIDTH 3 +/* Number PMU register started from PM0 passthrough to VM */ #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) +#define CSR_GCFG_GPERFP_SHIFT 23 +/* Read-only bit: show PMU passthrough supported or not */ +#define CSR_GCFG_GPERFP (_ULCAST_(0x1) << CSR_GCFG_GPERFP_SHIFT) #define CSR_GCFG_GCI_SHIFT 20 #define CSR_GCFG_GCI_WIDTH 2 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) +/* All cacheop instructions will trap to host */ #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) +/* Cacheop instruction except hit invalidate will trap to host */ #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) +/* Cacheop instruction except hit and index invalidate will trap to host */ #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) #define CSR_GCFG_GCIP_SHIFT 16 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) +/* Read-only bit: show feature CSR_GCFG_GCI_ALL supported or not */ #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) +/* Read-only bit: show feature CSR_GCFG_GCI_HIT supported or not */ #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) +/* Read-only bit: show feature CSR_GCFG_GCI_SECURE supported or not */ #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) #define CSR_GCFG_TORU_SHIFT 15 +/* Operation with CSR register unimplemented will trap to host */ #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) #define CSR_GCFG_TORUP_SHIFT 14 +/* Read-only bit: show feature CSR_GCFG_TORU supported or not */ #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) #define CSR_GCFG_TOP_SHIFT 13 +/* Modificattion with CRMD.PLV will trap to host */ #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) #define CSR_GCFG_TOPP_SHIFT 12 +/* Read-only bit: show feature CSR_GCFG_TOP supported or not */ #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) #define CSR_GCFG_TOE_SHIFT 11 +/* ertn instruction will trap to host */ #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) #define CSR_GCFG_TOEP_SHIFT 10 +/* Read-only bit: show feature CSR_GCFG_TOE supported or not */ #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) #define CSR_GCFG_TIT_SHIFT 9 +/* Timer instruction such as rdtime/TCFG/TVAL will trap to host */ #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) #define CSR_GCFG_TITP_SHIFT 8 +/* Read-only bit: show feature CSR_GCFG_TIT supported or not */ #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) #define CSR_GCFG_SIT_SHIFT 7 +/* All privilege instruction will trap to host */ #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) #define CSR_GCFG_SITP_SHIFT 6 +/* Read-only bit: show feature CSR_GCFG_SIT supported or not */ #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) #define CSR_GCFG_MATC_SHITF 4 #define CSR_GCFG_MATC_WIDTH 2 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) +/* Cache attribute comes from GVA->GPA mapping */ #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) +/* Cache attribute comes from GPA->HPA mapping */ #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) +/* Cache attribute comes from weaker one of GVA->GPA and GPA->HPA mapping */ #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) #define CSR_GCFG_MATP_NEST_SHIFT 2 +/* Read-only bit: show feature CSR_GCFG_MATC_NEST supported or not */ #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) #define CSR_GCFG_MATP_ROOT_SHIFT 1 +/* Read-only bit: show feature CSR_GCFG_MATC_ROOT supported or not */ #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) #define CSR_GCFG_MATP_GUEST_SHIFT 0 +/* Read-only bit: show feature CSR_GCFG_MATC_GUEST suppoorted or not */ #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c index bf9268bf26d5..f6d3242b9234 100644 --- a/arch/loongarch/kvm/main.c +++ b/arch/loongarch/kvm/main.c @@ -303,9 +303,9 @@ int kvm_arch_enable_virtualization_cpu(void) * TOE=0: Trap on Exception. * TIT=0: Trap on Timer. */ - if (env & CSR_GCFG_GCIP_ALL) + if (env & CSR_GCFG_GCIP_SECURE) gcfg |= CSR_GCFG_GCI_SECURE; - if (env & CSR_GCFG_MATC_ROOT) + if (env & CSR_GCFG_MATP_ROOT) gcfg |= CSR_GCFG_MATC_ROOT; write_csr_gcfg(gcfg); -- 2.39.3 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection 2025-02-07 3:26 ` [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection Bibo Mao @ 2025-02-09 9:38 ` Huacai Chen 2025-02-10 1:41 ` bibo mao 0 siblings, 1 reply; 10+ messages in thread From: Huacai Chen @ 2025-02-09 9:38 UTC (permalink / raw) To: Bibo Mao; +Cc: Tianrui Zhao, WANG Xuerui, kvm, loongarch, linux-kernel Hi, Bibo, On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: > > This is typo issue about GCFG feature macro, comments is added for > these macro and typo issue is fixed here. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++ > arch/loongarch/kvm/main.c | 4 ++-- > 2 files changed, 28 insertions(+), 2 deletions(-) > > diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h > index 52651aa0e583..1a65b5a7d54a 100644 > --- a/arch/loongarch/include/asm/loongarch.h > +++ b/arch/loongarch/include/asm/loongarch.h > @@ -502,49 +502,75 @@ > #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ > #define CSR_GCFG_GPERF_SHIFT 24 > #define CSR_GCFG_GPERF_WIDTH 3 > +/* Number PMU register started from PM0 passthrough to VM */ > #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) > +#define CSR_GCFG_GPERFP_SHIFT 23 > +/* Read-only bit: show PMU passthrough supported or not */ > +#define CSR_GCFG_GPERFP (_ULCAST_(0x1) << CSR_GCFG_GPERFP_SHIFT) > #define CSR_GCFG_GCI_SHIFT 20 > #define CSR_GCFG_GCI_WIDTH 2 > #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) > +/* All cacheop instructions will trap to host */ > #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) > +/* Cacheop instruction except hit invalidate will trap to host */ > #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) > +/* Cacheop instruction except hit and index invalidate will trap to host */ > #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) > #define CSR_GCFG_GCIP_SHIFT 16 > #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) > +/* Read-only bit: show feature CSR_GCFG_GCI_ALL supported or not */ > #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) > +/* Read-only bit: show feature CSR_GCFG_GCI_HIT supported or not */ > #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) > +/* Read-only bit: show feature CSR_GCFG_GCI_SECURE supported or not */ > #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) > #define CSR_GCFG_TORU_SHIFT 15 > +/* Operation with CSR register unimplemented will trap to host */ > #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) > #define CSR_GCFG_TORUP_SHIFT 14 > +/* Read-only bit: show feature CSR_GCFG_TORU supported or not */ > #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) > #define CSR_GCFG_TOP_SHIFT 13 > +/* Modificattion with CRMD.PLV will trap to host */ > #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) > #define CSR_GCFG_TOPP_SHIFT 12 > +/* Read-only bit: show feature CSR_GCFG_TOP supported or not */ > #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) > #define CSR_GCFG_TOE_SHIFT 11 > +/* ertn instruction will trap to host */ > #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) > #define CSR_GCFG_TOEP_SHIFT 10 > +/* Read-only bit: show feature CSR_GCFG_TOE supported or not */ > #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) > #define CSR_GCFG_TIT_SHIFT 9 > +/* Timer instruction such as rdtime/TCFG/TVAL will trap to host */ > #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) > #define CSR_GCFG_TITP_SHIFT 8 > +/* Read-only bit: show feature CSR_GCFG_TIT supported or not */ > #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) > #define CSR_GCFG_SIT_SHIFT 7 > +/* All privilege instruction will trap to host */ > #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) > #define CSR_GCFG_SITP_SHIFT 6 > +/* Read-only bit: show feature CSR_GCFG_SIT supported or not */ > #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) > #define CSR_GCFG_MATC_SHITF 4 > #define CSR_GCFG_MATC_WIDTH 2 > #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) > +/* Cache attribute comes from GVA->GPA mapping */ > #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) > +/* Cache attribute comes from GPA->HPA mapping */ > #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) > +/* Cache attribute comes from weaker one of GVA->GPA and GPA->HPA mapping */ > #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) > #define CSR_GCFG_MATP_NEST_SHIFT 2 > +/* Read-only bit: show feature CSR_GCFG_MATC_NEST supported or not */ > #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) > #define CSR_GCFG_MATP_ROOT_SHIFT 1 > +/* Read-only bit: show feature CSR_GCFG_MATC_ROOT supported or not */ > #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) > #define CSR_GCFG_MATP_GUEST_SHIFT 0 > +/* Read-only bit: show feature CSR_GCFG_MATC_GUEST suppoorted or not */ > #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) Bugfix is the majority here, so it is better to remove the comments, make this patch easier to be backported to stable branches. Huacai > > #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ > diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c > index bf9268bf26d5..f6d3242b9234 100644 > --- a/arch/loongarch/kvm/main.c > +++ b/arch/loongarch/kvm/main.c > @@ -303,9 +303,9 @@ int kvm_arch_enable_virtualization_cpu(void) > * TOE=0: Trap on Exception. > * TIT=0: Trap on Timer. > */ > - if (env & CSR_GCFG_GCIP_ALL) > + if (env & CSR_GCFG_GCIP_SECURE) > gcfg |= CSR_GCFG_GCI_SECURE; > - if (env & CSR_GCFG_MATC_ROOT) > + if (env & CSR_GCFG_MATP_ROOT) > gcfg |= CSR_GCFG_MATC_ROOT; > > write_csr_gcfg(gcfg); > -- > 2.39.3 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection 2025-02-09 9:38 ` Huacai Chen @ 2025-02-10 1:41 ` bibo mao 2025-02-10 3:58 ` Huacai Chen 0 siblings, 1 reply; 10+ messages in thread From: bibo mao @ 2025-02-10 1:41 UTC (permalink / raw) To: Huacai Chen; +Cc: Tianrui Zhao, WANG Xuerui, kvm, loongarch, linux-kernel On 2025/2/9 下午5:38, Huacai Chen wrote: > Hi, Bibo, > > On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: >> >> This is typo issue about GCFG feature macro, comments is added for >> these macro and typo issue is fixed here. >> >> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >> --- >> arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++ >> arch/loongarch/kvm/main.c | 4 ++-- >> 2 files changed, 28 insertions(+), 2 deletions(-) >> >> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h >> index 52651aa0e583..1a65b5a7d54a 100644 >> --- a/arch/loongarch/include/asm/loongarch.h >> +++ b/arch/loongarch/include/asm/loongarch.h >> @@ -502,49 +502,75 @@ >> #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ >> #define CSR_GCFG_GPERF_SHIFT 24 >> #define CSR_GCFG_GPERF_WIDTH 3 >> +/* Number PMU register started from PM0 passthrough to VM */ >> #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) >> +#define CSR_GCFG_GPERFP_SHIFT 23 >> +/* Read-only bit: show PMU passthrough supported or not */ >> +#define CSR_GCFG_GPERFP (_ULCAST_(0x1) << CSR_GCFG_GPERFP_SHIFT) >> #define CSR_GCFG_GCI_SHIFT 20 >> #define CSR_GCFG_GCI_WIDTH 2 >> #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) >> +/* All cacheop instructions will trap to host */ >> #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) >> +/* Cacheop instruction except hit invalidate will trap to host */ >> #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) >> +/* Cacheop instruction except hit and index invalidate will trap to host */ >> #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) >> #define CSR_GCFG_GCIP_SHIFT 16 >> #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) >> +/* Read-only bit: show feature CSR_GCFG_GCI_ALL supported or not */ >> #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) >> +/* Read-only bit: show feature CSR_GCFG_GCI_HIT supported or not */ >> #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) >> +/* Read-only bit: show feature CSR_GCFG_GCI_SECURE supported or not */ >> #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) >> #define CSR_GCFG_TORU_SHIFT 15 >> +/* Operation with CSR register unimplemented will trap to host */ >> #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) >> #define CSR_GCFG_TORUP_SHIFT 14 >> +/* Read-only bit: show feature CSR_GCFG_TORU supported or not */ >> #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) >> #define CSR_GCFG_TOP_SHIFT 13 >> +/* Modificattion with CRMD.PLV will trap to host */ >> #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) >> #define CSR_GCFG_TOPP_SHIFT 12 >> +/* Read-only bit: show feature CSR_GCFG_TOP supported or not */ >> #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) >> #define CSR_GCFG_TOE_SHIFT 11 >> +/* ertn instruction will trap to host */ >> #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) >> #define CSR_GCFG_TOEP_SHIFT 10 >> +/* Read-only bit: show feature CSR_GCFG_TOE supported or not */ >> #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) >> #define CSR_GCFG_TIT_SHIFT 9 >> +/* Timer instruction such as rdtime/TCFG/TVAL will trap to host */ >> #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) >> #define CSR_GCFG_TITP_SHIFT 8 >> +/* Read-only bit: show feature CSR_GCFG_TIT supported or not */ >> #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) >> #define CSR_GCFG_SIT_SHIFT 7 >> +/* All privilege instruction will trap to host */ >> #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) >> #define CSR_GCFG_SITP_SHIFT 6 >> +/* Read-only bit: show feature CSR_GCFG_SIT supported or not */ >> #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) >> #define CSR_GCFG_MATC_SHITF 4 >> #define CSR_GCFG_MATC_WIDTH 2 >> #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) >> +/* Cache attribute comes from GVA->GPA mapping */ >> #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) >> +/* Cache attribute comes from GPA->HPA mapping */ >> #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) >> +/* Cache attribute comes from weaker one of GVA->GPA and GPA->HPA mapping */ >> #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) >> #define CSR_GCFG_MATP_NEST_SHIFT 2 >> +/* Read-only bit: show feature CSR_GCFG_MATC_NEST supported or not */ >> #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) >> #define CSR_GCFG_MATP_ROOT_SHIFT 1 >> +/* Read-only bit: show feature CSR_GCFG_MATC_ROOT supported or not */ >> #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) >> #define CSR_GCFG_MATP_GUEST_SHIFT 0 >> +/* Read-only bit: show feature CSR_GCFG_MATC_GUEST suppoorted or not */ >> #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) > Bugfix is the majority here, so it is better to remove the comments, > make this patch easier to be backported to stable branches. How about split the patch into two for better backporting? With comments it is convinient to people to understand and provide LoongArch KVM patches in future, after all it cannot depends on the few guys inside. Regards Bibo Mao > > Huacai > >> >> #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ >> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c >> index bf9268bf26d5..f6d3242b9234 100644 >> --- a/arch/loongarch/kvm/main.c >> +++ b/arch/loongarch/kvm/main.c >> @@ -303,9 +303,9 @@ int kvm_arch_enable_virtualization_cpu(void) >> * TOE=0: Trap on Exception. >> * TIT=0: Trap on Timer. >> */ >> - if (env & CSR_GCFG_GCIP_ALL) >> + if (env & CSR_GCFG_GCIP_SECURE) >> gcfg |= CSR_GCFG_GCI_SECURE; >> - if (env & CSR_GCFG_MATC_ROOT) >> + if (env & CSR_GCFG_MATP_ROOT) >> gcfg |= CSR_GCFG_MATC_ROOT; >> >> write_csr_gcfg(gcfg); >> -- >> 2.39.3 >> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection 2025-02-10 1:41 ` bibo mao @ 2025-02-10 3:58 ` Huacai Chen 2025-02-10 6:32 ` bibo mao 0 siblings, 1 reply; 10+ messages in thread From: Huacai Chen @ 2025-02-10 3:58 UTC (permalink / raw) To: bibo mao; +Cc: Tianrui Zhao, WANG Xuerui, kvm, loongarch, linux-kernel On Mon, Feb 10, 2025 at 9:42 AM bibo mao <maobibo@loongson.cn> wrote: > > > > On 2025/2/9 下午5:38, Huacai Chen wrote: > > Hi, Bibo, > > > > On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: > >> > >> This is typo issue about GCFG feature macro, comments is added for > >> these macro and typo issue is fixed here. > >> > >> Signed-off-by: Bibo Mao <maobibo@loongson.cn> > >> --- > >> arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++ > >> arch/loongarch/kvm/main.c | 4 ++-- > >> 2 files changed, 28 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h > >> index 52651aa0e583..1a65b5a7d54a 100644 > >> --- a/arch/loongarch/include/asm/loongarch.h > >> +++ b/arch/loongarch/include/asm/loongarch.h > >> @@ -502,49 +502,75 @@ > >> #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ > >> #define CSR_GCFG_GPERF_SHIFT 24 > >> #define CSR_GCFG_GPERF_WIDTH 3 > >> +/* Number PMU register started from PM0 passthrough to VM */ > >> #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) > >> +#define CSR_GCFG_GPERFP_SHIFT 23 > >> +/* Read-only bit: show PMU passthrough supported or not */ > >> +#define CSR_GCFG_GPERFP (_ULCAST_(0x1) << CSR_GCFG_GPERFP_SHIFT) > >> #define CSR_GCFG_GCI_SHIFT 20 > >> #define CSR_GCFG_GCI_WIDTH 2 > >> #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) > >> +/* All cacheop instructions will trap to host */ > >> #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) > >> +/* Cacheop instruction except hit invalidate will trap to host */ > >> #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) > >> +/* Cacheop instruction except hit and index invalidate will trap to host */ > >> #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) > >> #define CSR_GCFG_GCIP_SHIFT 16 > >> #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) > >> +/* Read-only bit: show feature CSR_GCFG_GCI_ALL supported or not */ > >> #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) > >> +/* Read-only bit: show feature CSR_GCFG_GCI_HIT supported or not */ > >> #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) > >> +/* Read-only bit: show feature CSR_GCFG_GCI_SECURE supported or not */ > >> #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) > >> #define CSR_GCFG_TORU_SHIFT 15 > >> +/* Operation with CSR register unimplemented will trap to host */ > >> #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) > >> #define CSR_GCFG_TORUP_SHIFT 14 > >> +/* Read-only bit: show feature CSR_GCFG_TORU supported or not */ > >> #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) > >> #define CSR_GCFG_TOP_SHIFT 13 > >> +/* Modificattion with CRMD.PLV will trap to host */ > >> #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) > >> #define CSR_GCFG_TOPP_SHIFT 12 > >> +/* Read-only bit: show feature CSR_GCFG_TOP supported or not */ > >> #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) > >> #define CSR_GCFG_TOE_SHIFT 11 > >> +/* ertn instruction will trap to host */ > >> #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) > >> #define CSR_GCFG_TOEP_SHIFT 10 > >> +/* Read-only bit: show feature CSR_GCFG_TOE supported or not */ > >> #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) > >> #define CSR_GCFG_TIT_SHIFT 9 > >> +/* Timer instruction such as rdtime/TCFG/TVAL will trap to host */ > >> #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) > >> #define CSR_GCFG_TITP_SHIFT 8 > >> +/* Read-only bit: show feature CSR_GCFG_TIT supported or not */ > >> #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) > >> #define CSR_GCFG_SIT_SHIFT 7 > >> +/* All privilege instruction will trap to host */ > >> #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) > >> #define CSR_GCFG_SITP_SHIFT 6 > >> +/* Read-only bit: show feature CSR_GCFG_SIT supported or not */ > >> #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) > >> #define CSR_GCFG_MATC_SHITF 4 > >> #define CSR_GCFG_MATC_WIDTH 2 > >> #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) > >> +/* Cache attribute comes from GVA->GPA mapping */ > >> #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) > >> +/* Cache attribute comes from GPA->HPA mapping */ > >> #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) > >> +/* Cache attribute comes from weaker one of GVA->GPA and GPA->HPA mapping */ > >> #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) > >> #define CSR_GCFG_MATP_NEST_SHIFT 2 > >> +/* Read-only bit: show feature CSR_GCFG_MATC_NEST supported or not */ > >> #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) > >> #define CSR_GCFG_MATP_ROOT_SHIFT 1 > >> +/* Read-only bit: show feature CSR_GCFG_MATC_ROOT supported or not */ > >> #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) > >> #define CSR_GCFG_MATP_GUEST_SHIFT 0 > >> +/* Read-only bit: show feature CSR_GCFG_MATC_GUEST suppoorted or not */ > >> #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) > > Bugfix is the majority here, so it is better to remove the comments, > > make this patch easier to be backported to stable branches. > How about split the patch into two for better backporting? With comments > it is convinient to people to understand and provide LoongArch KVM > patches in future, after all it cannot depends on the few guys inside. I don't suggest splitting, just removing it is better (developers still need to read the user manual even if there are such comments). But if you insist, then keep it as is (keep this version). Huacai > > Regards > Bibo Mao > > > > Huacai > > > >> > >> #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ > >> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c > >> index bf9268bf26d5..f6d3242b9234 100644 > >> --- a/arch/loongarch/kvm/main.c > >> +++ b/arch/loongarch/kvm/main.c > >> @@ -303,9 +303,9 @@ int kvm_arch_enable_virtualization_cpu(void) > >> * TOE=0: Trap on Exception. > >> * TIT=0: Trap on Timer. > >> */ > >> - if (env & CSR_GCFG_GCIP_ALL) > >> + if (env & CSR_GCFG_GCIP_SECURE) > >> gcfg |= CSR_GCFG_GCI_SECURE; > >> - if (env & CSR_GCFG_MATC_ROOT) > >> + if (env & CSR_GCFG_MATP_ROOT) > >> gcfg |= CSR_GCFG_MATC_ROOT; > >> > >> write_csr_gcfg(gcfg); > >> -- > >> 2.39.3 > >> > > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection 2025-02-10 3:58 ` Huacai Chen @ 2025-02-10 6:32 ` bibo mao 0 siblings, 0 replies; 10+ messages in thread From: bibo mao @ 2025-02-10 6:32 UTC (permalink / raw) To: Huacai Chen; +Cc: Tianrui Zhao, WANG Xuerui, kvm, loongarch, linux-kernel On 2025/2/10 上午11:58, Huacai Chen wrote: > On Mon, Feb 10, 2025 at 9:42 AM bibo mao <maobibo@loongson.cn> wrote: >> >> >> >> On 2025/2/9 下午5:38, Huacai Chen wrote: >>> Hi, Bibo, >>> >>> On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: >>>> >>>> This is typo issue about GCFG feature macro, comments is added for >>>> these macro and typo issue is fixed here. >>>> >>>> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >>>> --- >>>> arch/loongarch/include/asm/loongarch.h | 26 ++++++++++++++++++++++++++ >>>> arch/loongarch/kvm/main.c | 4 ++-- >>>> 2 files changed, 28 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h >>>> index 52651aa0e583..1a65b5a7d54a 100644 >>>> --- a/arch/loongarch/include/asm/loongarch.h >>>> +++ b/arch/loongarch/include/asm/loongarch.h >>>> @@ -502,49 +502,75 @@ >>>> #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */ >>>> #define CSR_GCFG_GPERF_SHIFT 24 >>>> #define CSR_GCFG_GPERF_WIDTH 3 >>>> +/* Number PMU register started from PM0 passthrough to VM */ >>>> #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT) >>>> +#define CSR_GCFG_GPERFP_SHIFT 23 >>>> +/* Read-only bit: show PMU passthrough supported or not */ >>>> +#define CSR_GCFG_GPERFP (_ULCAST_(0x1) << CSR_GCFG_GPERFP_SHIFT) >>>> #define CSR_GCFG_GCI_SHIFT 20 >>>> #define CSR_GCFG_GCI_WIDTH 2 >>>> #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT) >>>> +/* All cacheop instructions will trap to host */ >>>> #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT) >>>> +/* Cacheop instruction except hit invalidate will trap to host */ >>>> #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT) >>>> +/* Cacheop instruction except hit and index invalidate will trap to host */ >>>> #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT) >>>> #define CSR_GCFG_GCIP_SHIFT 16 >>>> #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT) >>>> +/* Read-only bit: show feature CSR_GCFG_GCI_ALL supported or not */ >>>> #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT) >>>> +/* Read-only bit: show feature CSR_GCFG_GCI_HIT supported or not */ >>>> #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1)) >>>> +/* Read-only bit: show feature CSR_GCFG_GCI_SECURE supported or not */ >>>> #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2)) >>>> #define CSR_GCFG_TORU_SHIFT 15 >>>> +/* Operation with CSR register unimplemented will trap to host */ >>>> #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT) >>>> #define CSR_GCFG_TORUP_SHIFT 14 >>>> +/* Read-only bit: show feature CSR_GCFG_TORU supported or not */ >>>> #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT) >>>> #define CSR_GCFG_TOP_SHIFT 13 >>>> +/* Modificattion with CRMD.PLV will trap to host */ >>>> #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT) >>>> #define CSR_GCFG_TOPP_SHIFT 12 >>>> +/* Read-only bit: show feature CSR_GCFG_TOP supported or not */ >>>> #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT) >>>> #define CSR_GCFG_TOE_SHIFT 11 >>>> +/* ertn instruction will trap to host */ >>>> #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT) >>>> #define CSR_GCFG_TOEP_SHIFT 10 >>>> +/* Read-only bit: show feature CSR_GCFG_TOE supported or not */ >>>> #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT) >>>> #define CSR_GCFG_TIT_SHIFT 9 >>>> +/* Timer instruction such as rdtime/TCFG/TVAL will trap to host */ >>>> #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT) >>>> #define CSR_GCFG_TITP_SHIFT 8 >>>> +/* Read-only bit: show feature CSR_GCFG_TIT supported or not */ >>>> #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT) >>>> #define CSR_GCFG_SIT_SHIFT 7 >>>> +/* All privilege instruction will trap to host */ >>>> #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT) >>>> #define CSR_GCFG_SITP_SHIFT 6 >>>> +/* Read-only bit: show feature CSR_GCFG_SIT supported or not */ >>>> #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT) >>>> #define CSR_GCFG_MATC_SHITF 4 >>>> #define CSR_GCFG_MATC_WIDTH 2 >>>> #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF) >>>> +/* Cache attribute comes from GVA->GPA mapping */ >>>> #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF) >>>> +/* Cache attribute comes from GPA->HPA mapping */ >>>> #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF) >>>> +/* Cache attribute comes from weaker one of GVA->GPA and GPA->HPA mapping */ >>>> #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF) >>>> #define CSR_GCFG_MATP_NEST_SHIFT 2 >>>> +/* Read-only bit: show feature CSR_GCFG_MATC_NEST supported or not */ >>>> #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT) >>>> #define CSR_GCFG_MATP_ROOT_SHIFT 1 >>>> +/* Read-only bit: show feature CSR_GCFG_MATC_ROOT supported or not */ >>>> #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT) >>>> #define CSR_GCFG_MATP_GUEST_SHIFT 0 >>>> +/* Read-only bit: show feature CSR_GCFG_MATC_GUEST suppoorted or not */ >>>> #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT) >>> Bugfix is the majority here, so it is better to remove the comments, >>> make this patch easier to be backported to stable branches. >> How about split the patch into two for better backporting? With comments >> it is convinient to people to understand and provide LoongArch KVM >> patches in future, after all it cannot depends on the few guys inside. > I don't suggest splitting, just removing it is better (developers > still need to read the user manual even if there are such comments). > But if you insist, then keep it as is (keep this version). Ok, I will remove comments . Put it in header file seems a temporary method :( Regards Bibo Mao > > > > Huacai >> >> Regards >> Bibo Mao >>> >>> Huacai >>> >>>> >>>> #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */ >>>> diff --git a/arch/loongarch/kvm/main.c b/arch/loongarch/kvm/main.c >>>> index bf9268bf26d5..f6d3242b9234 100644 >>>> --- a/arch/loongarch/kvm/main.c >>>> +++ b/arch/loongarch/kvm/main.c >>>> @@ -303,9 +303,9 @@ int kvm_arch_enable_virtualization_cpu(void) >>>> * TOE=0: Trap on Exception. >>>> * TIT=0: Trap on Timer. >>>> */ >>>> - if (env & CSR_GCFG_GCIP_ALL) >>>> + if (env & CSR_GCFG_GCIP_SECURE) >>>> gcfg |= CSR_GCFG_GCI_SECURE; >>>> - if (env & CSR_GCFG_MATC_ROOT) >>>> + if (env & CSR_GCFG_MATP_ROOT) >>>> gcfg |= CSR_GCFG_MATC_ROOT; >>>> >>>> write_csr_gcfg(gcfg); >>>> -- >>>> 2.39.3 >>>> >> >> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] LoongArch: KVM: Remove duplicated cache attribute setting 2025-02-07 3:26 [PATCH 0/3] LoongArch: KVM: Some tiny code cleanup Bibo Mao 2025-02-07 3:26 ` [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection Bibo Mao @ 2025-02-07 3:26 ` Bibo Mao 2025-02-07 3:26 ` [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode Bibo Mao 2 siblings, 0 replies; 10+ messages in thread From: Bibo Mao @ 2025-02-07 3:26 UTC (permalink / raw) To: Tianrui Zhao; +Cc: Huacai Chen, WANG Xuerui, kvm, loongarch, linux-kernel Cache attribute comes from GPA->HPA secondary mmu page table and is configured when kvm is enabled. It is the same for all VMs, remove duplicated cache attribute setting on vCPU context switch. Signed-off-by: Bibo Mao <maobibo@loongson.cn> --- arch/loongarch/kvm/vcpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index fb72095c8077..20f941af3e9e 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -1548,9 +1548,6 @@ static int _kvm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) /* Restore timer state regardless */ kvm_restore_timer(vcpu); - - /* Control guest page CCA attribute */ - change_csr_gcfg(CSR_GCFG_MATC_MASK, CSR_GCFG_MATC_ROOT); kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu); /* Restore hardware PMU CSRs */ -- 2.39.3 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode 2025-02-07 3:26 [PATCH 0/3] LoongArch: KVM: Some tiny code cleanup Bibo Mao 2025-02-07 3:26 ` [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection Bibo Mao 2025-02-07 3:26 ` [PATCH 2/3] LoongArch: KVM: Remove duplicated cache attribute setting Bibo Mao @ 2025-02-07 3:26 ` Bibo Mao 2025-02-09 9:47 ` Huacai Chen 2 siblings, 1 reply; 10+ messages in thread From: Bibo Mao @ 2025-02-07 3:26 UTC (permalink / raw) To: Tianrui Zhao; +Cc: Huacai Chen, WANG Xuerui, kvm, loongarch, linux-kernel PRMD and ERA register is only meaningful on the beginning stage of exception entry, and it can be overwritten for nested irq or exception. When CPU runs in VM mode, interrupt need be enabled on host. And the mode for host had better be kernel mode rather than random. Signed-off-by: Bibo Mao <maobibo@loongson.cn> --- arch/loongarch/kvm/switch.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S index 0c292f818492..1be185e94807 100644 --- a/arch/loongarch/kvm/switch.S +++ b/arch/loongarch/kvm/switch.S @@ -85,7 +85,7 @@ * Guest CRMD comes from separate GCSR_CRMD register */ ori t0, zero, CSR_PRMD_PIE - csrxchg t0, t0, LOONGARCH_CSR_PRMD + csrwr t0, LOONGARCH_CSR_PRMD /* Set PVM bit to setup ertn to guest context */ ori t0, zero, CSR_GSTAT_PVM -- 2.39.3 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode 2025-02-07 3:26 ` [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode Bibo Mao @ 2025-02-09 9:47 ` Huacai Chen 2025-02-10 1:43 ` bibo mao 0 siblings, 1 reply; 10+ messages in thread From: Huacai Chen @ 2025-02-09 9:47 UTC (permalink / raw) To: Bibo Mao; +Cc: Tianrui Zhao, WANG Xuerui, kvm, loongarch, linux-kernel Hi, Bibo, On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: > > PRMD and ERA register is only meaningful on the beginning stage > of exception entry, and it can be overwritten for nested irq or > exception. The code doesn't touch ERA, so ERA in the commit message is a typo? Huacai > > When CPU runs in VM mode, interrupt need be enabled on host. And the > mode for host had better be kernel mode rather than random. > > Signed-off-by: Bibo Mao <maobibo@loongson.cn> > --- > arch/loongarch/kvm/switch.S | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S > index 0c292f818492..1be185e94807 100644 > --- a/arch/loongarch/kvm/switch.S > +++ b/arch/loongarch/kvm/switch.S > @@ -85,7 +85,7 @@ > * Guest CRMD comes from separate GCSR_CRMD register > */ > ori t0, zero, CSR_PRMD_PIE > - csrxchg t0, t0, LOONGARCH_CSR_PRMD > + csrwr t0, LOONGARCH_CSR_PRMD > > /* Set PVM bit to setup ertn to guest context */ > ori t0, zero, CSR_GSTAT_PVM > -- > 2.39.3 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode 2025-02-09 9:47 ` Huacai Chen @ 2025-02-10 1:43 ` bibo mao 0 siblings, 0 replies; 10+ messages in thread From: bibo mao @ 2025-02-10 1:43 UTC (permalink / raw) To: Huacai Chen; +Cc: Tianrui Zhao, WANG Xuerui, kvm, loongarch, linux-kernel On 2025/2/9 下午5:47, Huacai Chen wrote: > Hi, Bibo, > > On Fri, Feb 7, 2025 at 11:26 AM Bibo Mao <maobibo@loongson.cn> wrote: >> >> PRMD and ERA register is only meaningful on the beginning stage >> of exception entry, and it can be overwritten for nested irq or >> exception. > The code doesn't touch ERA, so ERA in the commit message is a typo? oh, ERA is redundant here. Will remove it in next version. Regards Bibo Mao > > Huacai >> >> When CPU runs in VM mode, interrupt need be enabled on host. And the >> mode for host had better be kernel mode rather than random. >> >> Signed-off-by: Bibo Mao <maobibo@loongson.cn> >> --- >> arch/loongarch/kvm/switch.S | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/loongarch/kvm/switch.S b/arch/loongarch/kvm/switch.S >> index 0c292f818492..1be185e94807 100644 >> --- a/arch/loongarch/kvm/switch.S >> +++ b/arch/loongarch/kvm/switch.S >> @@ -85,7 +85,7 @@ >> * Guest CRMD comes from separate GCSR_CRMD register >> */ >> ori t0, zero, CSR_PRMD_PIE >> - csrxchg t0, t0, LOONGARCH_CSR_PRMD >> + csrwr t0, LOONGARCH_CSR_PRMD >> >> /* Set PVM bit to setup ertn to guest context */ >> ori t0, zero, CSR_GSTAT_PVM >> -- >> 2.39.3 >> ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-02-10 6:33 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-02-07 3:26 [PATCH 0/3] LoongArch: KVM: Some tiny code cleanup Bibo Mao 2025-02-07 3:26 ` [PATCH 1/3] LoongArch: KVM: Fix typo issue about GCFG feature detection Bibo Mao 2025-02-09 9:38 ` Huacai Chen 2025-02-10 1:41 ` bibo mao 2025-02-10 3:58 ` Huacai Chen 2025-02-10 6:32 ` bibo mao 2025-02-07 3:26 ` [PATCH 2/3] LoongArch: KVM: Remove duplicated cache attribute setting Bibo Mao 2025-02-07 3:26 ` [PATCH 3/3] LoongArch: KVM: Set host with kernel mode when switch to VM mode Bibo Mao 2025-02-09 9:47 ` Huacai Chen 2025-02-10 1:43 ` bibo mao
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