Re: [PATCH] phy: qcom-snps: Correct the FSEL_MASK

[Stephen Boyd <swboyd@chromium.org>]

Quoting Sandeep Maheswaram (2021-10-19 23:36:25)
> The FSEL_MASK which selects the refclock is defined incorrectly.
> It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7)
> in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 is reset which keeps PHY analog
> blocks ON during suspend.
> Fix this issue by correctly defining the FSEL_MASK.
>
> Signed-off-by: Sandeep Maheswaram <quic_c_sanm@quicinc.com>

Any Fixes tag?

> ---
>  drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
> index ae4bac0..28459a1 100644
> --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /*
>   * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.

I never thought I'd see this again! :)

>   */
>
>  #include <linux/clk.h>
> @@ -33,7 +34,7 @@
>
>  #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0   (0x54)
>  #define RETENABLEN                             BIT(3)
> -#define FSEL_MASK                              GENMASK(7, 5)
> +#define FSEL_MASK                              GENMASK(6, 4)
>  #define FSEL_DEFAULT                           (0x3 << 4)
>
>  #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1   (0x58)