From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: magnus.damm@gmail.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, biju.das.jz@bp.renesas.com,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
Date: Tue, 3 Mar 2026 15:20:23 +0100 [thread overview]
Message-ID: <CAMuHMdWsTqVEc3DFvgSZxTvF_F+Us5-RtKa88TYN1S_fGjdEHQ@mail.gmail.com> (raw)
In-Reply-To: <20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com>
On Mon, 2 Mar 2026 at 14:57, Claudiu <claudiu.beznea@tuxon.dev> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The default settings for the Versa3 device on the Renesas RZ/G3S SMARC
> SoM board have PLL2 disabled. PLL2 was later enabled together with audio
> support, as it is required to support both 44.1 kHz and 48 kHz audio.
>
> With PLL2 enabled, it was observed that Linux occasionally either hangs
> during boot (the last log message being related to the I2C probe) or
> randomly crashes. This was mainly reproducible on cold boots. During
> debugging, it was also noticed that the Unicode replacement character (�)
> sometimes appears on the serial console. Further investigation traced this
> to the configuration applied through the Versa3 register at offset 0x1c,
> which controls PLL enablement.
>
> The appearance of the Unicode replacement character suggested an issue
> with the SoC reference clock. The RZ/G3S reference clock is provided by
> the Versa3 clock generator (REF output).
>
> After checking with the Renesas Versa3 hardware team, it was found that
> this is related to the PLL2 lock bit being set through the
> renesas,settings DT property.
>
> The PLL lock bit must be set to avoid unstable clock output from the PLL.
> However, due to the Versa3 hardware design, when a PLL lock bit is set,
> all outputs (including the REF clock) are temporarily disabled until the
> configured PLLs become stable.
>
> As an alternative, the bypass bit can be used. This does not interrupt the
> PLL2 output or any other Versa3 outputs, but it may result in temporary
> instability on PLL2 output while the configuration is applied. Since PLL2
> feeds only the audio path and audio is not used during early boot, this is
> acceptable and does not affect system boot.
>
> Drop the PLL2 lock bit and set the bypass bit instead.
>
> This has been tested with more than 1000 cold boots.
>
> Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-fixes for v7.0.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
prev parent reply other threads:[~2026-03-03 14:20 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 13:57 Claudiu
2026-03-03 14:20 ` Geert Uytterhoeven [this message]
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