* [PATCH 1/4] gpu: nova-core: Extract PFSP register definitions
2026-08-25 23:44 [PATCH 0/4] gpu: nova-core: Extract falcon registers Antonin Malzieu Ridolfi via B4 Relay
@ 2026-08-25 23:44 ` Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 2/4] gpu: nova-core: falcon: Extract PRISCV register Antonin Malzieu Ridolfi via B4 Relay
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-08-25 23:44 UTC (permalink / raw)
To: Danilo Krummrich, Alice Ryhl, Alexandre Courbot, David Airlie,
Simona Vetter
Cc: linux-kernel, nova-gpu, dri-devel, Antonin Malzieu Ridolfi
From: Antonin Malzieu Ridolfi <dev@nanonej.com>
Move PFSP register definitions from the root regs.rs file into the
falcon module that own them, in the new falcon/regs.rs file.
This follows the same pattern established by previous commits for
GSP, PDISP, PFB, PBUS and PMC registers: register definitions move to
the module that interprets their service, visibility changes to
pub(super).
Since PFALCON registers are defined in the root regs.rs but are
also part of the falcon interface, accessed by the whole falcon
module. They are re-exported in falcon/regs.rs so falcon code can use
a single regs:: prefix.
Once the PFALCON family moves out of the root module, these
re-exports will become plain definitions.
Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
---
| 4 ++--
| 6 +++---
| 39 ++++++++++++++++++++++++++++++++++++
| 21 -------------------
4 files changed, 44 insertions(+), 26 deletions(-)
--git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 11c1008b7d1e..68658a6e666c 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -32,13 +32,13 @@
num::{
self,
FromSafeCast, //
- },
- regs,
+ }, //
};
pub(crate) mod fsp;
pub(crate) mod gsp;
mod hal;
+mod regs;
pub(crate) mod sec2;
/// Alignment (in bytes) of falcon memory blocks.
--git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs
index 0437180b8829..c2bc61ecc07c 100644
--- a/drivers/gpu/nova-core/falcon/fsp.rs
+++ b/drivers/gpu/nova-core/falcon/fsp.rs
@@ -23,13 +23,13 @@
use crate::{
falcon::{
+ regs, //
Falcon,
FalconEngine,
PFalcon2Base,
- PFalconBase, //
+ PFalconBase,
},
- num,
- regs, //
+ num, //
};
/// FSP message timeout in milliseconds.
--git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs
new file mode 100644
index 000000000000..96e1f0f1df5a
--- /dev/null
+++ b/drivers/gpu/nova-core/falcon/regs.rs
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
+
+use kernel::io::register;
+
+// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust.
+// These registers manage falcon EMEM communication queues.
+
+register! {
+ pub(super) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 {
+ 31:0 address => u32;
+ }
+
+ pub(super) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 {
+ 31:0 address => u32;
+ }
+
+ pub(super) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 {
+ 31:0 val => u32;
+ }
+
+ pub(super) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 {
+ 31:0 val => u32;
+ }
+}
+
+// PFALCON registers are defined in the root `regs.rs` but are part of the falcon
+// interface, accessed by the whole falcon module. They are re-exported here so
+// falcon code can use a single `regs::` prefix.
+// Once the PFALCON family moves out of the root module, these re-exports become
+// plain definitions.
+pub(super) use crate::regs::{
+ NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS,
+ NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1,
+ NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS,
+ NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC,
+ NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IMEMD,
+ NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON_MAILBOX1,
+ NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PFALCON_FBIF_TRANSCFG,
+};
--git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 3422b49df7a7..0404fb82aa7e 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -359,27 +359,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
}
}
-// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust.
-// These registers manage falcon EMEM communication queues.
-
-register! {
- pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 {
- 31:0 address => u32;
- }
-
- pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 {
- 31:0 address => u32;
- }
-
- pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 {
- 31:0 val => u32;
- }
-
- pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 {
- 31:0 val => u32;
- }
-}
-
// The modules below provide registers that are not identical on all supported chips. They should
// only be used in HAL modules.
--
2.55.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 2/4] gpu: nova-core: falcon: Extract PRISCV register
2026-08-25 23:44 [PATCH 0/4] gpu: nova-core: Extract falcon registers Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 1/4] gpu: nova-core: Extract PFSP register definitions Antonin Malzieu Ridolfi via B4 Relay
@ 2026-08-25 23:44 ` Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 3/4] gpu: nova-core: falcon: Extract PFALCON2 register Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 4/4] gpu: nova-core: Extract PFALCON register Antonin Malzieu Ridolfi via B4 Relay
3 siblings, 0 replies; 7+ messages in thread
From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-08-25 23:44 UTC (permalink / raw)
To: Danilo Krummrich, Alice Ryhl, Alexandre Courbot, David Airlie,
Simona Vetter
Cc: linux-kernel, nova-gpu, dri-devel, Antonin Malzieu Ridolfi
From: Antonin Malzieu Ridolfi <dev@nanonej.com>
Move PRISCV register definitions from the root regs.rs file into the
falcon module that own them, in the existing falcon/regs.rs file.
This follows the same pattern established by previous commits for
GSP, PDISP, PFB, PBUS, PMC and PFSP registers: register definitions
move to the module that interprets their service, visibility changes
to pub(super).
Since PFALCON, PFALCON2 and FUSE registers are defined in the root
regs.rs but are also part of the falcon interface, accessed by the
whole falcon module. They are re-exported in falcon/regs.rs so falcon
code can use a single regs:: prefix.
Once these families moves out of the root module, these re-exports
will become plain definitions.
Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
---
| 4 +--
| 12 +++----
| 56 +++++++++++++++++++++++++------
| 27 +--------------
4 files changed, 53 insertions(+), 46 deletions(-)
--git a/drivers/gpu/nova-core/falcon/hal/ga102.rs b/drivers/gpu/nova-core/falcon/hal/ga102.rs
index 7600ee07ca2e..7586f80388b0 100644
--- a/drivers/gpu/nova-core/falcon/hal/ga102.rs
+++ b/drivers/gpu/nova-core/falcon/hal/ga102.rs
@@ -20,13 +20,13 @@
driver::Bar0,
falcon::{
hal::LoadMethod,
+ regs, //
Falcon,
FalconBromParams,
FalconEngine,
FalconModSelAlgo,
- PeregrineCoreSelect, //
+ PeregrineCoreSelect,
},
- regs,
};
use super::FalconHal;
--git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-core/falcon/hal/tu102.rs
index 5291598fedf7..fb624b925f49 100644
--- a/drivers/gpu/nova-core/falcon/hal/tu102.rs
+++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs
@@ -12,14 +12,12 @@
time::Delta, //
};
-use crate::{
- falcon::{
- hal::LoadMethod,
- Falcon,
- FalconBromParams,
- FalconEngine, //
- },
+use crate::falcon::{
+ hal::LoadMethod,
regs, //
+ Falcon,
+ FalconBromParams,
+ FalconEngine,
};
use super::FalconHal;
--git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs
index 96e1f0f1df5a..a9e1f75598dd 100644
--- a/drivers/gpu/nova-core/falcon/regs.rs
+++ b/drivers/gpu/nova-core/falcon/regs.rs
@@ -2,6 +2,35 @@
use kernel::io::register;
+use crate::falcon::{
+ PFalcon2Base,
+ PeregrineCoreSelect, //
+};
+
+// PRISCV
+
+register! {
+ /// RISC-V status register for debug (Turing and GA100 only).
+ /// Reflects current RISC-V core status.
+ pub(super) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 {
+ /// RISC-V core active/inactive status.
+ 0:0 active_stat => bool;
+ }
+
+ /// GA102 and later.
+ pub(super) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 {
+ 7:7 active_stat => bool;
+ 4:4 halted => bool;
+ }
+
+ /// GA102 and later.
+ pub(super) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 {
+ 8:8 br_fetch => bool;
+ 4:4 core_select => PeregrineCoreSelect;
+ 0:0 valid => bool;
+ }
+}
+
// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust.
// These registers manage falcon EMEM communication queues.
@@ -23,17 +52,22 @@
}
}
-// PFALCON registers are defined in the root `regs.rs` but are part of the falcon
-// interface, accessed by the whole falcon module. They are re-exported here so
-// falcon code can use a single `regs::` prefix.
-// Once the PFALCON family moves out of the root module, these re-exports become
+// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` but
+// are part of the falcon interface, accessed by the whole falcon module. They
+// are re-exported here so falcon code can use a single `regs::` prefix.
+// Once these families move out of the root module, these re-exports become
// plain definitions.
pub(super) use crate::regs::{
- NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS,
- NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1,
- NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS,
- NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC,
- NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IMEMD,
- NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON_MAILBOX1,
- NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PFALCON_FBIF_TRANSCFG,
+ NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION,
+ NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE,
+ NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMASK,
+ NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALCON_FALCON_BOOTVEC,
+ NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_FALCON_DMACTL,
+ NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCON_FALCON_DMATRFCMD,
+ NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFALCON_FALCON_DMEMC,
+ NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EMEMD,
+ NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_IMEMC,
+ NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0,
+ NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL,
+ NV_PFALCON_FBIF_TRANSCFG,
};
--git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 0404fb82aa7e..5c1cef1c66a1 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -24,8 +24,7 @@
FalconModSelAlgo,
FalconSecurityModel,
PFalcon2Base,
- PFalconBase,
- PeregrineCoreSelect, //
+ PFalconBase, //
},
};
@@ -335,30 +334,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
}
}
-// PRISCV
-
-register! {
- /// RISC-V status register for debug (Turing and GA100 only).
- /// Reflects current RISC-V core status.
- pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 {
- /// RISC-V core active/inactive status.
- 0:0 active_stat => bool;
- }
-
- /// GA102 and later.
- pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 {
- 7:7 active_stat => bool;
- 4:4 halted => bool;
- }
-
- /// GA102 and later.
- pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 {
- 8:8 br_fetch => bool;
- 4:4 core_select => PeregrineCoreSelect;
- 0:0 valid => bool;
- }
-}
-
// The modules below provide registers that are not identical on all supported chips. They should
// only be used in HAL modules.
--
2.55.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/4] gpu: nova-core: falcon: Extract PFALCON2 register
2026-08-25 23:44 [PATCH 0/4] gpu: nova-core: Extract falcon registers Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 1/4] gpu: nova-core: Extract PFSP register definitions Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 2/4] gpu: nova-core: falcon: Extract PRISCV register Antonin Malzieu Ridolfi via B4 Relay
@ 2026-08-25 23:44 ` Antonin Malzieu Ridolfi via B4 Relay
2026-08-25 23:44 ` [PATCH 4/4] gpu: nova-core: Extract PFALCON register Antonin Malzieu Ridolfi via B4 Relay
3 siblings, 0 replies; 7+ messages in thread
From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-08-25 23:44 UTC (permalink / raw)
To: Danilo Krummrich, Alice Ryhl, Alexandre Courbot, David Airlie,
Simona Vetter
Cc: linux-kernel, nova-gpu, dri-devel, Antonin Malzieu Ridolfi
From: Antonin Malzieu Ridolfi <dev@nanonej.com>
Move PFALCON2 register definitions from the root regs.rs file into
the falcon module that own them, in the existing falcon/regs.rs file.
This follows the same pattern established by previous commits for
GSP, PDISP, PFB, PBUS, PMC, PFSP and PRISCV registers: register
definitions move to the module that interprets their service,
visibility changes to pub(super).
Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
---
| 4 ++--
| 31 ++++++++++++++++++++++++++-----
| 24 ------------------------
3 files changed, 28 insertions(+), 31 deletions(-)
--git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 68658a6e666c..11613a2ccb69 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -95,8 +95,8 @@ pub(crate) enum FalconSecurityModel with TryFrom<Bounded<u32, 2>> {
bounded_enum! {
/// Signing algorithm for a given firmware, used in the
- /// [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon Boot ROM
- /// (BROM) as a parameter.
+ /// [`crate::falcon::regs::NV_PFALCON2_FALCON_MOD_SEL`] register. It is passed to the Falcon
+ /// Boot ROM (BROM) as a parameter.
#[derive(Debug, Copy, Clone)]
pub(crate) enum FalconModSelAlgo with TryFrom<Bounded<u32, 8>> {
/// AES.
--git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs
index a9e1f75598dd..446a67bdf3dd 100644
--- a/drivers/gpu/nova-core/falcon/regs.rs
+++ b/drivers/gpu/nova-core/falcon/regs.rs
@@ -3,10 +3,33 @@
use kernel::io::register;
use crate::falcon::{
+ FalconModSelAlgo,
PFalcon2Base,
PeregrineCoreSelect, //
};
+// PFALCON2
+
+register! {
+ pub(super) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 {
+ 7:0 algo ?=> FalconModSelAlgo;
+ }
+
+ pub(super) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 {
+ 7:0 ucode_id => u8;
+ }
+
+ pub(super) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c {
+ 31:0 value => u32;
+ }
+
+ /// OpenRM defines this as a register array, but doesn't specify its size and only uses its
+ /// first element. Be conservative until we know the actual size or need to use more registers.
+ pub(super) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 {
+ 31:0 value => u32;
+ }
+}
+
// PRISCV
register! {
@@ -52,16 +75,14 @@
}
}
-// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` but
-// are part of the falcon interface, accessed by the whole falcon module. They
+// PFALCON and FUSE registers are defined in the root `regs.rs` but are
+// part of the falcon interface, accessed by the whole falcon module. They
// are re-exported here so falcon code can use a single `regs::` prefix.
// Once these families move out of the root module, these re-exports become
// plain definitions.
pub(super) use crate::regs::{
NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION,
- NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE,
- NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMASK,
- NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALCON_FALCON_BOOTVEC,
+ NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, NV_PFALCON_FALCON_BOOTVEC,
NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_FALCON_DMACTL,
NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCON_FALCON_DMATRFCMD,
NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFALCON_FALCON_DMEMC,
--git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index 5c1cef1c66a1..c9eca3ff911f 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -21,9 +21,7 @@
FalconFbifMemType,
FalconFbifTarget,
FalconMem,
- FalconModSelAlgo,
FalconSecurityModel,
- PFalcon2Base,
PFalconBase, //
},
};
@@ -312,28 +310,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
}
}
-/* PFALCON2 */
-
-register! {
- pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 {
- 7:0 algo ?=> FalconModSelAlgo;
- }
-
- pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 {
- 7:0 ucode_id => u8;
- }
-
- pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c {
- 31:0 value => u32;
- }
-
- /// OpenRM defines this as a register array, but doesn't specify its size and only uses its
- /// first element. Be conservative until we know the actual size or need to use more registers.
- pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 {
- 31:0 value => u32;
- }
-}
-
// The modules below provide registers that are not identical on all supported chips. They should
// only be used in HAL modules.
--
2.55.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 4/4] gpu: nova-core: Extract PFALCON register
2026-08-25 23:44 [PATCH 0/4] gpu: nova-core: Extract falcon registers Antonin Malzieu Ridolfi via B4 Relay
` (2 preceding siblings ...)
2026-08-25 23:44 ` [PATCH 3/4] gpu: nova-core: falcon: Extract PFALCON2 register Antonin Malzieu Ridolfi via B4 Relay
@ 2026-08-25 23:44 ` Antonin Malzieu Ridolfi via B4 Relay
2026-08-28 1:12 ` Alexandre Courbot
3 siblings, 1 reply; 7+ messages in thread
From: Antonin Malzieu Ridolfi via B4 Relay @ 2026-08-25 23:44 UTC (permalink / raw)
To: Danilo Krummrich, Alice Ryhl, Alexandre Courbot, David Airlie,
Simona Vetter
Cc: linux-kernel, nova-gpu, dri-devel, Antonin Malzieu Ridolfi
From: Antonin Malzieu Ridolfi <dev@nanonej.com>
Move PFALCON register definitions from the root regs.rs file into the
falcon module that own them, in the existing falcon/regs.rs file.
This follows the same pattern established by previous commits for
GSP, PDISP, PFB, PBUS, PMC, PFSP, PRISCV and PFALCON2 registers:
register definitions move to the module that interprets their
service, visibility changes to pub(super).
The firmware module still needs to configure the FBIF DMA index used
by the bootloader to fetch the FWSEC firmware from system memory, so
the falcon module now exposes a `set_fbif_transcfg_regs_at()` helper
to access the `NV_PFALCON_FBIF_TRANSCFG` register.
Suggested-by: Alexandre Courbot <acourbot@nvidia.com>
Suggested-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Antonin Malzieu Ridolfi <dev@nanonej.com>
---
| 30 ++-
| 16 +-
| 248 +++++++++++++++++++--
| 22 +-
| 7 +-
| 225 +------------------
6 files changed, 263 insertions(+), 285 deletions(-)
--git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 11613a2ccb69..d2ee9876bafb 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -45,8 +45,8 @@
pub(crate) const MEM_BLOCK_ALIGNMENT: usize = 256;
bounded_enum! {
- /// Revision number of a falcon core, used in the [`crate::regs::NV_PFALCON_FALCON_HWCFG1`]
- /// register.
+ /// Revision number of a falcon core, used in the
+ /// [`crate::falcon::regs::NV_PFALCON_FALCON_HWCFG1`] register.
#[derive(Debug, Copy, Clone)]
pub(crate) enum FalconCoreRev with TryFrom<Bounded<u32, 4>> {
Rev1 = 1,
@@ -61,7 +61,7 @@ pub(crate) enum FalconCoreRev with TryFrom<Bounded<u32, 4>> {
bounded_enum! {
/// Revision subversion number of a falcon core, used in the
- /// [`crate::regs::NV_PFALCON_FALCON_HWCFG1`] register.
+ /// [`crate::falcon::regs::NV_PFALCON_FALCON_HWCFG1`] register.
#[derive(Debug, Copy, Clone)]
pub(crate) enum FalconCoreRevSubversion with From<Bounded<u32, 2>> {
Subversion0 = 0,
@@ -107,8 +107,8 @@ pub(crate) enum FalconModSelAlgo with TryFrom<Bounded<u32, 8>> {
}
bounded_enum! {
- /// Valid values for the `size` field of the [`crate::regs::NV_PFALCON_FALCON_DMATRFCMD`]
- /// register.
+ /// Valid values for the `size` field of the
+ /// [`crate::falcon::regs::NV_PFALCON_FALCON_DMATRFCMD`] register.
#[derive(Debug, Copy, Clone)]
pub(crate) enum DmaTrfCmdSize with TryFrom<Bounded<u32, 3>> {
/// 256 bytes transfer.
@@ -592,6 +592,20 @@ fn dma_wr(
Ok(())
}
+ // Configure DMA index for the bootloader to fetch the FWSEC firmware from system memory.
+ pub(crate) fn set_fbif_transcfg_regs_at(&self, ctx_dma: u32) -> Result {
+ self.bar.update(
+ regs::NV_PFALCON_FBIF_TRANSCFG::of::<E>()
+ .try_at(usize::from_safe_cast(ctx_dma))
+ .ok_or(EINVAL)?,
+ |v| {
+ v.with_target(FalconFbifTarget::CoherentSysmem)
+ .with_mem_type(FalconFbifMemType::Physical)
+ },
+ );
+ Ok(())
+ }
+
/// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the falcon to run it.
fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(&self, fw: &F) -> Result {
// DMA object with firmware content as the source of the DMA engine.
@@ -614,11 +628,7 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(&self, fw: &F) ->
};
self.dma_reset();
- self.bar
- .update(regs::NV_PFALCON_FBIF_TRANSCFG::of::<E>().at(0), |v| {
- v.with_target(FalconFbifTarget::CoherentSysmem)
- .with_mem_type(FalconFbifMemType::Physical)
- });
+ self.set_fbif_transcfg_regs_at(0)?;
self.dma_wr(&dma_obj, FalconMem::ImemSecure, fw.imem_sec_load_params())?;
self.dma_wr(&dma_obj, FalconMem::Dmem, fw.dmem_load_params())?;
--git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs
index ae32f401aeb0..fec13f5e99f4 100644
--- a/drivers/gpu/nova-core/falcon/gsp.rs
+++ b/drivers/gpu/nova-core/falcon/gsp.rs
@@ -7,20 +7,18 @@
RegisterBase,
WithBase, //
},
- Io,
+ Io, //
},
prelude::*,
time::Delta, //
};
-use crate::{
- falcon::{
- Falcon,
- FalconEngine,
- PFalcon2Base,
- PFalconBase, //
- },
+use crate::falcon::{
regs,
+ Falcon,
+ FalconEngine,
+ PFalcon2Base,
+ PFalconBase, //
};
/// Type specifying the `Gsp` falcon engine. Cannot be instantiated.
@@ -49,7 +47,7 @@ pub(crate) fn clear_swgen0_intr(&self) {
/// Checks if GSP reload/resume has completed during the boot process.
pub(crate) fn check_reload_completed(&self, timeout: Delta) -> Result<bool> {
read_poll_timeout(
- || Ok(self.bar.read(regs::NV_PGC6_BSI_SECURE_SCRATCH_14)),
+ || Ok(self.bar.read(crate::regs::NV_PGC6_BSI_SECURE_SCRATCH_14)),
|val| val.boot_stage_3_handoff(),
Delta::ZERO,
timeout,
--git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs
index 446a67bdf3dd..8e82d9f439a9 100644
--- a/drivers/gpu/nova-core/falcon/regs.rs
+++ b/drivers/gpu/nova-core/falcon/regs.rs
@@ -1,13 +1,233 @@
// SPDX-License-Identifier: GPL-2.0
-use kernel::io::register;
+use kernel::{
+ io::{
+ register,
+ register::WithBase,
+ Io, //
+ },
+ time, //
+};
-use crate::falcon::{
- FalconModSelAlgo,
- PFalcon2Base,
- PeregrineCoreSelect, //
+use crate::{
+ driver::Bar0,
+ falcon::{
+ DmaTrfCmdSize,
+ FalconCoreRev,
+ FalconCoreRevSubversion,
+ FalconEngine,
+ FalconFbifMemType,
+ FalconFbifTarget,
+ FalconMem,
+ FalconModSelAlgo,
+ FalconSecurityModel,
+ PFalcon2Base,
+ PFalconBase,
+ PeregrineCoreSelect, //
+ },
};
+// PFALCON
+
+register! {
+ pub(super) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 {
+ 6:6 swgen0 => bool;
+ 4:4 halt => bool;
+ }
+
+ pub(super) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 {
+ 31:0 value => u32;
+ }
+
+ pub(super) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 {
+ 31:0 value => u32;
+ }
+
+ /// Used to store version information about the firmware running
+ /// on the Falcon processor.
+ pub(super) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 {
+ 31:0 value => u32;
+ }
+
+ pub(super) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 {
+ 31:0 value => u32;
+ }
+
+ pub(super) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 {
+ /// Signal indicating that reset is completed (GA102+).
+ 31:31 reset_ready => bool;
+ /// RISC-V branch privilege lockdown bit.
+ 13:13 riscv_br_priv_lockdown => bool;
+ /// Set to 0 after memory scrubbing is completed.
+ 12:12 mem_scrubbing => bool;
+ 10:10 riscv => bool;
+ }
+
+ pub(super) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 {
+ 6:6 alias_en => bool;
+ 4:4 halted => bool;
+ 1:1 startcpu => bool;
+ }
+
+ pub(super) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 {
+ 31:0 value => u32;
+ }
+
+ pub(super) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c {
+ 7:7 secure_stat => bool;
+ 6:3 dmaq_num;
+ 2:2 imem_scrubbing => bool;
+ 1:1 dmem_scrubbing => bool;
+ 0:0 require_ctx => bool;
+ }
+
+ pub(super) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x00000110 {
+ 31:0 base => u32;
+ }
+
+ pub(super) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x00000114 {
+ 23:0 offs;
+ }
+
+ pub(super) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118 {
+ 16:16 set_dmtag;
+ 14:12 ctxdma;
+ 10:8 size ?=> DmaTrfCmdSize;
+ 5:5 is_write => bool;
+ 4:4 imem => bool;
+ 3:2 sec;
+ 1:1 idle => bool;
+ 0:0 full => bool;
+ }
+
+ pub(super) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x0000011c {
+ 31:0 offs => u32;
+ }
+
+ pub(super) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x00000128 {
+ 8:0 base;
+ }
+
+ pub(super) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c {
+ /// Core revision subversion.
+ 7:6 core_rev_subversion => FalconCoreRevSubversion;
+ /// Security model.
+ 5:4 security_model ?=> FalconSecurityModel;
+ /// Core revision.
+ 3:0 core_rev ?=> FalconCoreRev;
+ }
+
+ pub(super) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000130 {
+ 1:1 startcpu => bool;
+ }
+
+ /// IMEM access control register. Up to 4 ports are available for IMEM access.
+ pub(super) NV_PFALCON_FALCON_IMEMC(u32)[4, stride = 16] @ PFalconBase + 0x00000180 {
+ /// Access secure IMEM.
+ 28:28 secure => bool;
+ /// Auto-increment on write.
+ 24:24 aincw => bool;
+ /// IMEM block and word offset.
+ 15:0 offs;
+ }
+
+ /// IMEM data register. Reading/writing this register accesses IMEM at the address
+ /// specified by the corresponding IMEMC register.
+ pub(super) NV_PFALCON_FALCON_IMEMD(u32)[4, stride = 16] @ PFalconBase + 0x00000184 {
+ 31:0 data;
+ }
+
+ /// IMEM tag register. Used to set the tag for the current IMEM block.
+ pub(super) NV_PFALCON_FALCON_IMEMT(u32)[4, stride = 16] @ PFalconBase + 0x00000188 {
+ 15:0 tag;
+ }
+
+ /// DMEM access control register. Up to 8 ports are available for DMEM access.
+ pub(super) NV_PFALCON_FALCON_DMEMC(u32)[8, stride = 8] @ PFalconBase + 0x000001c0 {
+ /// Auto-increment on write.
+ 24:24 aincw => bool;
+ /// DMEM block and word offset.
+ 15:0 offs;
+ }
+
+ /// DMEM data register. Reading/writing this register accesses DMEM at the address
+ /// specified by the corresponding DMEMC register.
+ pub(super) NV_PFALCON_FALCON_DMEMD(u32)[8, stride = 8] @ PFalconBase + 0x000001c4 {
+ 31:0 data;
+ }
+
+ /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the
+ /// falcon instance.
+ pub(super) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 {
+ 0:0 reset => bool;
+ }
+
+ pub(super) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600 {
+ 2:2 mem_type => FalconFbifMemType;
+ 1:0 target ?=> FalconFbifTarget;
+ }
+
+ pub(super) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 {
+ 7:7 allow_phys_no_ctx => bool;
+ }
+
+ // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell).
+ // These provide the falcon external memory communication interface.
+
+ pub(super) NV_PFALCON_FALCON_EMEMC(u32) @ PFalconBase + 0x00000ac0 {
+ /// EMEM byte offset (4-byte aligned) within the block.
+ 7:2 offs;
+ /// EMEM block to access.
+ 15:8 blk;
+ /// Auto-increment the offset after each write.
+ 24:24 aincw => bool;
+ /// Auto-increment the offset after each read.
+ 25:25 aincr => bool;
+ }
+
+ pub(super) NV_PFALCON_FALCON_EMEMD(u32) @ PFalconBase + 0x00000ac4 {
+ 31:0 data => u32;
+ }
+}
+
+impl NV_PFALCON_FALCON_DMACTL {
+ /// Returns `true` if memory scrubbing is completed.
+ pub(super) fn mem_scrubbing_done(self) -> bool {
+ !self.dmem_scrubbing() && !self.imem_scrubbing()
+ }
+}
+
+impl NV_PFALCON_FALCON_DMATRFCMD {
+ /// Programs the `imem` and `sec` fields for the given FalconMem
+ pub(super) fn with_falcon_mem(self, mem: FalconMem) -> Self {
+ let this = self.with_imem(mem != FalconMem::Dmem);
+
+ match mem {
+ FalconMem::ImemSecure => this.with_const_sec::<1>(),
+ _ => this.with_const_sec::<0>(),
+ }
+ }
+}
+
+impl NV_PFALCON_FALCON_ENGINE {
+ /// Resets the falcon
+ pub(super) fn reset_engine<E: FalconEngine>(bar: Bar0<'_>) {
+ bar.update(Self::of::<E>(), |r| r.with_reset(true));
+
+ // TIMEOUT: falcon engine should not take more than 10us to reset.
+ time::delay::fsleep(time::Delta::from_micros(10));
+
+ bar.update(Self::of::<E>(), |r| r.with_reset(false));
+ }
+}
+
+impl NV_PFALCON_FALCON_HWCFG2 {
+ /// Returns `true` if memory scrubbing is completed.
+ pub(super) fn mem_scrubbing_done(self) -> bool {
+ !self.mem_scrubbing()
+ }
+}
+
// PFALCON2
register! {
@@ -75,20 +295,10 @@
}
}
-// PFALCON and FUSE registers are defined in the root `regs.rs` but are
-// part of the falcon interface, accessed by the whole falcon module. They
-// are re-exported here so falcon code can use a single `regs::` prefix.
-// Once these families move out of the root module, these re-exports become
-// plain definitions.
+// FUSE registers are defined in the root `regs.rs` but are part of the
+// falcon interface, accessed by the whole falcon module. They are
+// re-exported here so falcon code can use a single `regs::` prefix.
pub(super) use crate::regs::{
NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION,
- NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE, NV_PFALCON_FALCON_BOOTVEC,
- NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_FALCON_DMACTL,
- NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCON_FALCON_DMATRFCMD,
- NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFALCON_FALCON_DMEMC,
- NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EMEMD,
- NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_IMEMC,
- NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0,
- NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL,
- NV_PFALCON_FBIF_TRANSCFG,
+ NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE,
};
--git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
index ec4d92317a93..6777e041c879 100644
--- a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
+++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
@@ -12,7 +12,6 @@
Device, //
},
dma::Coherent,
- io::{register::WithBase, Io},
prelude::*,
ptr::{
Alignable,
@@ -23,15 +22,12 @@
};
use crate::{
- driver::Bar0,
falcon::{
self,
gsp::Gsp,
Falcon,
FalconBromParams,
FalconDmaLoadable,
- FalconFbifMemType,
- FalconFbifTarget,
FalconFirmware,
FalconPioDmemLoadTarget,
FalconPioImemLoadTarget,
@@ -46,7 +42,6 @@
},
gpu::Chipset,
num::FromSafeCast, //
- regs,
};
/// Structure used by the boot-loader to load the rest of the code.
@@ -235,12 +230,7 @@ pub(crate) fn new(
///
/// The bootloader will load the FWSEC firmware and then execute it. This function returns
/// after FWSEC has reached completion.
- pub(crate) fn run(
- &self,
- dev: &Device<device::Bound>,
- falcon: &Falcon<'_, Gsp>,
- bar: Bar0<'_>,
- ) -> Result<()> {
+ pub(crate) fn run(&self, dev: &Device<device::Bound>, falcon: &Falcon<'_, Gsp>) -> Result<()> {
// Reset falcon, load the firmware, and run it.
falcon
.reset()
@@ -250,15 +240,7 @@ pub(crate) fn run(
.inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware: {:?}\n", e))?;
// Configure DMA index for the bootloader to fetch the FWSEC firmware from system memory.
- bar.update(
- regs::NV_PFALCON_FBIF_TRANSCFG::of::<Gsp>()
- .try_at(usize::from_safe_cast(self.dmem_desc.ctx_dma))
- .ok_or(EINVAL)?,
- |v| {
- v.with_target(FalconFbifTarget::CoherentSysmem)
- .with_mem_type(FalconFbifMemType::Physical)
- },
- );
+ falcon.set_fbif_transcfg_regs_at(self.dmem_desc.ctx_dma)?;
let (mbox0, _) = falcon
.boot(Some(0), None)
--git a/drivers/gpu/nova-core/gsp/hal/tu102.rs b/drivers/gpu/nova-core/gsp/hal/tu102.rs
index a5c0ca355493..d2ef35080689 100644
--- a/drivers/gpu/nova-core/gsp/hal/tu102.rs
+++ b/drivers/gpu/nova-core/gsp/hal/tu102.rs
@@ -62,12 +62,11 @@ impl FwsecUnloadFirmware {
fn run(
&self,
dev: &device::Device<device::Bound>,
- bar: Bar0<'_>,
gsp_falcon: &Falcon<'_, GspEngine>,
) -> Result {
match self {
Self::WithoutBl(fw) => fw.run(dev, gsp_falcon),
- Self::WithBl(fw) => fw.run(dev, gsp_falcon, bar),
+ Self::WithBl(fw) => fw.run(dev, gsp_falcon),
}
}
}
@@ -88,7 +87,7 @@ fn run(&self, ctx: &mut GspBootContext<'_, '_>) -> Result {
// Log errors but keep going if it fails.
let fwsec_sb_res = self
.fwsec_sb
- .run(dev, bar, ctx.gsp_falcon)
+ .run(dev, ctx.gsp_falcon)
.inspect_err(|e| dev_err!(dev, "FWSEC-SB failed to run: {:?}\n", e));
// Remove WPR2 region if set.
@@ -168,7 +167,7 @@ fn run_fwsec_frts(
if self.needs_fwsec_bootloader {
let fwsec_frts_bl = FwsecFirmwareWithBl::new(fwsec_frts, dev, chipset)?;
// Load and run the bootloader, which will load FWSEC-FRTS and run it.
- fwsec_frts_bl.run(dev, falcon, bar)?;
+ fwsec_frts_bl.run(dev, falcon)?;
} else {
// Load and run FWSEC-FRTS directly.
fwsec_frts.run(dev, falcon)?;
--git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index c9eca3ff911f..842664428b0d 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -2,28 +2,8 @@
// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
use kernel::{
- io::{
- register,
- register::WithBase,
- Io, //
- },
- sizes::SizeConstants,
- time, //
-};
-
-use crate::{
- driver::Bar0,
- falcon::{
- DmaTrfCmdSize,
- FalconCoreRev,
- FalconCoreRevSubversion,
- FalconEngine,
- FalconFbifMemType,
- FalconFbifTarget,
- FalconMem,
- FalconSecurityModel,
- PFalconBase, //
- },
+ io::register,
+ sizes::SizeConstants, //
};
// PBUS
@@ -109,207 +89,6 @@ pub(crate) fn usable_fb_size(self) -> u64 {
}
}
-// PFALCON
-
-register! {
- pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 {
- 6:6 swgen0 => bool;
- 4:4 halt => bool;
- }
-
- pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 {
- 31:0 value => u32;
- }
-
- pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 {
- 31:0 value => u32;
- }
-
- /// Used to store version information about the firmware running
- /// on the Falcon processor.
- pub(crate) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 {
- 31:0 value => u32;
- }
-
- pub(crate) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 {
- 31:0 value => u32;
- }
-
- pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 {
- /// Signal indicating that reset is completed (GA102+).
- 31:31 reset_ready => bool;
- /// RISC-V branch privilege lockdown bit.
- 13:13 riscv_br_priv_lockdown => bool;
- /// Set to 0 after memory scrubbing is completed.
- 12:12 mem_scrubbing => bool;
- 10:10 riscv => bool;
- }
-
- pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 {
- 6:6 alias_en => bool;
- 4:4 halted => bool;
- 1:1 startcpu => bool;
- }
-
- pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 {
- 31:0 value => u32;
- }
-
- pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c {
- 7:7 secure_stat => bool;
- 6:3 dmaq_num;
- 2:2 imem_scrubbing => bool;
- 1:1 dmem_scrubbing => bool;
- 0:0 require_ctx => bool;
- }
-
- pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x00000110 {
- 31:0 base => u32;
- }
-
- pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x00000114 {
- 23:0 offs;
- }
-
- pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118 {
- 16:16 set_dmtag;
- 14:12 ctxdma;
- 10:8 size ?=> DmaTrfCmdSize;
- 5:5 is_write => bool;
- 4:4 imem => bool;
- 3:2 sec;
- 1:1 idle => bool;
- 0:0 full => bool;
- }
-
- pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x0000011c {
- 31:0 offs => u32;
- }
-
- pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x00000128 {
- 8:0 base;
- }
-
- pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c {
- /// Core revision subversion.
- 7:6 core_rev_subversion => FalconCoreRevSubversion;
- /// Security model.
- 5:4 security_model ?=> FalconSecurityModel;
- /// Core revision.
- 3:0 core_rev ?=> FalconCoreRev;
- }
-
- pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000130 {
- 1:1 startcpu => bool;
- }
-
- /// IMEM access control register. Up to 4 ports are available for IMEM access.
- pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride = 16] @ PFalconBase + 0x00000180 {
- /// Access secure IMEM.
- 28:28 secure => bool;
- /// Auto-increment on write.
- 24:24 aincw => bool;
- /// IMEM block and word offset.
- 15:0 offs;
- }
-
- /// IMEM data register. Reading/writing this register accesses IMEM at the address
- /// specified by the corresponding IMEMC register.
- pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride = 16] @ PFalconBase + 0x00000184 {
- 31:0 data;
- }
-
- /// IMEM tag register. Used to set the tag for the current IMEM block.
- pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride = 16] @ PFalconBase + 0x00000188 {
- 15:0 tag;
- }
-
- /// DMEM access control register. Up to 8 ports are available for DMEM access.
- pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride = 8] @ PFalconBase + 0x000001c0 {
- /// Auto-increment on write.
- 24:24 aincw => bool;
- /// DMEM block and word offset.
- 15:0 offs;
- }
-
- /// DMEM data register. Reading/writing this register accesses DMEM at the address
- /// specified by the corresponding DMEMC register.
- pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride = 8] @ PFalconBase + 0x000001c4 {
- 31:0 data;
- }
-
- /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the
- /// falcon instance.
- pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 {
- 0:0 reset => bool;
- }
-
- pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600 {
- 2:2 mem_type => FalconFbifMemType;
- 1:0 target ?=> FalconFbifTarget;
- }
-
- pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 {
- 7:7 allow_phys_no_ctx => bool;
- }
-
- // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell).
- // These provide the falcon external memory communication interface.
-
- pub(crate) NV_PFALCON_FALCON_EMEMC(u32) @ PFalconBase + 0x00000ac0 {
- /// EMEM byte offset (4-byte aligned) within the block.
- 7:2 offs;
- /// EMEM block to access.
- 15:8 blk;
- /// Auto-increment the offset after each write.
- 24:24 aincw => bool;
- /// Auto-increment the offset after each read.
- 25:25 aincr => bool;
- }
-
- pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ PFalconBase + 0x00000ac4 {
- 31:0 data => u32;
- }
-}
-
-impl NV_PFALCON_FALCON_DMACTL {
- /// Returns `true` if memory scrubbing is completed.
- pub(crate) fn mem_scrubbing_done(self) -> bool {
- !self.dmem_scrubbing() && !self.imem_scrubbing()
- }
-}
-
-impl NV_PFALCON_FALCON_DMATRFCMD {
- /// Programs the `imem` and `sec` fields for the given FalconMem
- pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self {
- let this = self.with_imem(mem != FalconMem::Dmem);
-
- match mem {
- FalconMem::ImemSecure => this.with_const_sec::<1>(),
- _ => this.with_const_sec::<0>(),
- }
- }
-}
-
-impl NV_PFALCON_FALCON_ENGINE {
- /// Resets the falcon
- pub(crate) fn reset_engine<E: FalconEngine>(bar: Bar0<'_>) {
- bar.update(Self::of::<E>(), |r| r.with_reset(true));
-
- // TIMEOUT: falcon engine should not take more than 10us to reset.
- time::delay::fsleep(time::Delta::from_micros(10));
-
- bar.update(Self::of::<E>(), |r| r.with_reset(false));
- }
-}
-
-impl NV_PFALCON_FALCON_HWCFG2 {
- /// Returns `true` if memory scrubbing is completed.
- pub(crate) fn mem_scrubbing_done(self) -> bool {
- !self.mem_scrubbing()
- }
-}
-
// The modules below provide registers that are not identical on all supported chips. They should
// only be used in HAL modules.
--
2.55.0
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