[PATCH v5 0/7] describe RTL8125 PCIe NICs on Rockchip boards (and add DT binding)

[PATCH v5 0/7] describe RTL8125 PCIe NICs on Rockchip boards (and add DT binding)

[Ricardo Pardini via B4 Relay]

Several Rockchip rk35xx boards carry on-board Realtek RTL8125 2.5GbE
NICs whose PCI function nodes are not described in the DT. Describing
them allows for stable ethernetN aliases (matching the GMAC alias
convention on these boards) and lets U-Boot's fdt_fixup_ethernet()
inject mac-address properties from its ethaddr/ethNaddr env, so MACs
stay stable across boots and U-Boot and kernel MAC match.

Tested on a NanoPC-T6: /sys/bus/pci/devices/0004:41:00.0/of_node ->
/sys/firmware/devicetree/base/pcie@fe190000/pcie@0,0/ethernet@0,0 and
u-boot correctly adds local-mac-address property there which is
correctly picked up kernel-side:

  => setenv eth1addr 8e:b4:90:66:66:66
  => boot
  ...
  # readlink -f /sys/bus/pci/devices/0004:41:00.0/of_node
  /sys/firmware/devicetree/base/pcie@fe190000/pcie@0,0/ethernet@0,0
  # xxd /sys/bus/pci/devices/0004:41:00.0/of_node/local-mac-address
  00000000: 8eb4 9066 6666                           ...fff
  # ip link show dev end1 | grep ether
       link/ether 8e:b4:90:66:66:66 brd ff:ff:ff:ff:ff:ff

Patch 1 adds a DT binding for Realtek RTL8125 family PCIe Ethernet
controllers.

Patch 2-7 describes the on-board RTL8125 function nodes on a few
Rockchip boards.

---
Changes in v5:
- binding: reword commit message: pci10ec,8125 is already covered by
  dtschema pci-device.yaml; the binding is added only to validate the
  ethernet-controller properties on these nodes (local-mac-address,
  nvmem-cells, et al) (ref Krzysztof, Heiner).
- boards: add a few more Rockchip boards with RTL8125's.
- Link to v4: https://patch.msgid.link/20260617-rk3588-dts-rtl-eth-describe-dt-alias-v4-0-2bd38922d129@pardini.net

Changes in v4:
- binding: simplify the binding YAML ref Sashiko's and Krzysztof's
  reviews
- binding: describe only the RTL8125 + rename to match ref Heiner's
  review.
- dt: fix the bus-range according to Sashiko's review.
- Link to v3: https://patch.msgid.link/20260605-rk3588-dts-rtl-eth-describe-dt-alias-v3-0-8a8857b39daf@pardini.net

Changes in v3:
- new patch: add a DT binding for Realtek r8169 family PCIe Ethernet
  controllers, per Sebastian Reichel's review (the "pciVVVV,DDDD" OF
  spelling still needs a binding when used in a board DT).
- new patch for Rock5 series, and include a brief rationale in each.
- retitle the series, since it now covers a few boards and a binding
  rather than just DeviceTree changes for the NanoPC-T6.
- drop the v2 "rename vcc3v3_pcie2x1l0 regulator" patch from this
  series; it will be sent separately as it is not relevant to this.
- Link to v2: https://patch.msgid.link/20260529-rk3588-dts-rtl-eth-describe-dt-alias-v2-0-49700248143f@pardini.net

Changes in v2:
- fix: pcie2x1l0, not pcie2x1l1; indirectly caught by Sashiko's review [1]
- while-at-it: rename regulator vcc3v3_pcie2x1l0 to l1
- Link to v1: https://patch.msgid.link/20260525-rk3588-dts-rtl-eth-describe-dt-alias-v1-1-a6fcda563ac7@pardini.net

[1] https://sashiko.dev/#/patchset/20260525-rk3588-dts-rtl-eth-describe-dt-alias-v1-1-a6fcda563ac7%40pardini.net

To: Heiner Kallweit <hkallweit1@gmail.com>
To: nic_swsd@realtek.com
To: Andrew Lunn <andrew+netdev@lunn.ch>
To: "David S. Miller" <davem@davemloft.net>
To: Eric Dumazet <edumazet@google.com>
To: Jakub Kicinski <kuba@kernel.org>
To: Paolo Abeni <pabeni@redhat.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Sebastian Reichel <sebastian.reichel@collabora.com>
Cc: netdev@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>

---
Ricardo Pardini (7):
      dt-bindings: net: add Realtek RTL8125 PCIe Ethernet
      arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6
      arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family
      arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588-NAS
      arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S
      arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C
      arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX

 .../devicetree/bindings/net/realtek,rtl8125.yaml   | 43 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 30 +++++++++++++++
 .../rockchip/rk3588-friendlyelec-cm3588-nas.dts    | 21 +++++++++++
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 +++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 30 +++++++++++++++
 .../boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi   | 15 ++++++++
 arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts    | 18 +++++++++
 .../arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 21 +++++++++++
 9 files changed, 209 insertions(+)
---
base-commit: df2908090cda368b01ff43709f51890076c56157
change-id: 20260524-rk3588-dts-rtl-eth-describe-dt-alias-c1ed187b7c50

Best regards,
--  
Ricardo Pardini <ricardo@pardini.net>

[PATCH v5 1/7] dt-bindings: net: add Realtek RTL8125 PCIe Ethernet

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

Add a binding for fixed/soldered Realtek RTL8125 PCIe Ethernet
controller. As a PCIe device, its "pci10ec,8125" compatible is the
Open Firmware spelling auto-derived from its PCI-SIG vendor/device IDs
and is already covered by the generic dtschema pci-device.yaml. The
compatible itself therefore needs no binding to be valid.

A dedicated binding is needed because board DTs describe these
soldered function nodes in order to attach ethernet-controller
properties to them: a placeholder local-mac-address that the bootloader
fills in today, and potentially nvmem-cells, phy-handle, etc. in the
future. This binding references ethernet-controller.yaml so those
properties are validated on the RTL8125 PCI function nodes.

Suggested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 .../devicetree/bindings/net/realtek,rtl8125.yaml   | 43 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 44 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/realtek,rtl8125.yaml b/Documentation/devicetree/bindings/net/realtek,rtl8125.yaml
new file mode 100644
index 0000000000000..eee13fbc1e6a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/realtek,rtl8125.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/realtek,rtl8125.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek RTL8125 2.5 Gigabit PCIe Ethernet Controller
+
+maintainers:
+  - Heiner Kallweit <hkallweit1@gmail.com>
+
+description:
+  The Realtek RTL8125 is a 2.5GBASE-T Ethernet controller with a PCIe host
+  interface.
+
+allOf:
+  - $ref: ethernet-controller.yaml#
+
+properties:
+  compatible:
+    const: pci10ec,8125
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    pcie {
+        #address-cells = <3>;
+        #size-cells = <2>;
+
+        ethernet@0,0 {
+            compatible = "pci10ec,8125";
+            reg = <0x10000 0 0 0 0>;
+            local-mac-address = [00 00 00 00 00 00];
+        };
+    };
diff --git a/MAINTAINERS b/MAINTAINERS
index 6215fcb077705..f74c559a3fd06 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -134,6 +134,7 @@ M:	Heiner Kallweit <hkallweit1@gmail.com>
 M:	nic_swsd@realtek.com
 L:	netdev@vger.kernel.org
 S:	Maintained
+F:	Documentation/devicetree/bindings/net/realtek,rtl8125.yaml
 F:	drivers/net/ethernet/realtek/r8169*
 
 8250/16?50 (AND CLONE UARTS) SERIAL DRIVER

-- 
2.55.0

[PATCH v5 2/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs
behind pcie2x1l0 and pcie2x1l2.

Describe the fixed function nodes and attach ethernet0/ethernet1
aliases, so that U-Boot's fdt_fixup_ethernet() can fill in the MAC
from its ethaddr/eth1addr env. The on-NIC EEPROMs on this board are
not pre-programmed with a unique MAC, so this gives a stable MAC
across boots that both U-Boot and the kernel agree on.

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
index cfdb5c13f8606..550358a756618 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
@@ -20,6 +20,8 @@ / {
 	compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
 
 	aliases {
+		ethernet0 = &rtl_eth0;
+		ethernet1 = &rtl_eth1;
 		mmc0 = &sdhci;
 		mmc1 = &sdmmc;
 	};
@@ -644,6 +646,20 @@ &pcie2x1l0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie2_0_rst>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x200000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x21 0x2f>;
+
+		rtl_eth0: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x210000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie2x1l1 {
@@ -660,6 +676,20 @@ &pcie2x1l2 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pcie2_2_rst>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x41 0x4f>;
+
+		rtl_eth1: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x410000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie30phy {

-- 
2.55.0

[PATCH v5 3/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 family

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

The Radxa ROCK 5B / 5B+ / 5T all carry on-board Realtek RTL8125 NICs.

Describe the fixed function nodes and attach ethernet0/ethernet1 aliases,
so that U-Boot's fdt_fixup_ethernet() can fill in the MAC from its
ethaddr/eth1addr env, for stable MACs across boots that both U-Boot
and the kernel agree on.

The RTL8125 on pcie2x1l2 is shared by all three variants. The ROCK 5T
additionally describes pcie2x1l1 with its second RTL8125.

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 .../arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 15 +++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts        | 18 ++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
index 13aaf63ad0936..fd0520b47ddb8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi
@@ -10,6 +10,7 @@
 
 / {
 	aliases {
+		ethernet0 = &rtl_eth0;
 		mmc0 = &sdhci;
 		mmc1 = &sdmmc;
 		mmc2 = &sdio;
@@ -488,6 +489,20 @@ &pcie2x1l2 {
 	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x41 0x4f>;
+
+		rtl_eth0: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x410000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie30phy {
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
index 425036146b6d9..b1a3e4b2165f9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts
@@ -8,6 +8,10 @@ / {
 	model = "Radxa ROCK 5T";
 	compatible = "radxa,rock-5t", "rockchip,rk3588";
 
+	aliases {
+		ethernet1 = &rtl_eth1;
+	};
+
 	analog-sound {
 		compatible = "audio-graph-card";
 		label = "rk3588-es8316";
@@ -76,6 +80,20 @@ &pcie2x1l1 {
 	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie2x1l1>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x31 0x3f>;
+
+		rtl_eth1: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x310000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie30phy {

-- 
2.55.0

[PATCH v5 4/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on CM3588-NAS

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

The FriendlyElec CM3588-NAS carrier carries an on-board Realtek
RTL8125 NIC behind pcie2x1l2.

Describe the fixed function node and attach an ethernet0 alias in the
NAS carrier .dts (not the SoM dtsi, as the RTL8125 sits on the
carrier), so that U-Boot's fdt_fixup_ethernet() can inject a
mac-address from its ethaddr env, for a stable MAC across boots that
both U-Boot and the kernel agree on.

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 .../dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
index f4c34da61c4df..96b3b245e0866 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-friendlyelec-cm3588-nas.dts
@@ -20,6 +20,10 @@ / {
 	model = "FriendlyElec CM3588 NAS";
 	compatible = "friendlyarm,cm3588-nas", "friendlyarm,cm3588", "rockchip,rk3588";
 
+	aliases {
+		ethernet0 = &rtl_eth0;
+	};
+
 	adc_key_recovery: adc-key-recovery {
 		compatible = "adc-keys";
 		io-channels = <&saradc 1>;
@@ -512,6 +516,23 @@ &pcie2x1l1 {
 	status = "okay";
 };
 
+&pcie2x1l2 {
+	/* on-board RTL8125 2.5GbE NIC */
+	pcie@0,0 {
+		reg = <0x400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x40 0x4f>;
+
+		rtl_eth0: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x410000 0 0 0 0>;
+		};
+	};
+};
+
 &pcie30phy {
 	/*
 	* Data lane mapping <1 3 2 4> = x1x1 x1x1 (bifurcation of both ports)

-- 
2.55.0

[PATCH v5 5/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R5S

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

The FriendlyElec NanoPi R5S (rk3568) carries two on-board Realtek
RTL8125 NICs behind pcie2x1 and pcie3x1, alongside the existing gmac0
RGMII PHY.

Describe the fixed function nodes and attach ethernet1/ethernet2
aliases (ethernet0 stays mapped to gmac0), so that U-Boot's
fdt_fixup_ethernet() can inject mac-address properties from its
eth1addr/eth2addr env, for stable MACs across boots that both U-Boot
and the kernel agree on.

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
index 90ce6f0e1dcff..9ed11663c31c9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@@ -15,6 +15,8 @@ / {
 
 	aliases {
 		ethernet0 = &gmac0;
+		ethernet1 = &rtl_eth1;
+		ethernet2 = &rtl_eth2;
 	};
 
 	gpio-keys {
@@ -107,6 +109,20 @@ &pcie2x1 {
 	num-lanes = <1>;
 	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x000000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x00 0x0f>;
+
+		rtl_eth1: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x010000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie30phy {
@@ -119,6 +135,20 @@ &pcie3x1 {
 	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x100000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x10 0x1f>;
+
+		rtl_eth2: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x110000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie3x2 {

-- 
2.55.0

[PATCH v5 6/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPi R6C

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

The FriendlyElec NanoPi R6C carries one on-board Realtek RTL8125 NIC
(the LAN port; WAN uses the on-SoC gmac1 RGMII PHY) behind pcie2x1l1.

Describe the fixed function node and attach an ethernet1 alias
(ethernet0 stays mapped to gmac1), so that U-Boot's fdt_fixup_ethernet()
can inject a mac-address from its eth1addr env, for a stable MAC
across boots that both U-Boot and the kernel agree on.

The function node is added in this .dts (not the shared
rk3588s-nanopi-r6.dtsi), since on the R6C the dtsi's second
RTL8125-capable lane is empty compared to the R6S.

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
index ccc5e46275176..b142df0b0e180 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
@@ -7,8 +7,29 @@
 / {
 	model = "FriendlyElec NanoPi R6C";
 	compatible = "friendlyarm,nanopi-r6c", "rockchip,rk3588s";
+
+	aliases {
+		ethernet1 = &rtl_eth1;
+	};
 };
 
 &lan2_led {
 	label = "user_led";
 };
+
+&pcie2x1l1 {
+	/* on-board RTL8125 2.5GbE NIC */
+	pcie@0,0 {
+		reg = <0x300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x30 0x3f>;
+
+		rtl_eth1: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x310000 0 0 0 0>;
+		};
+	};
+};

-- 
2.55.0

[PATCH v5 7/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on ROCK 5 ITX

[Ricardo Pardini via B4 Relay]

From: Ricardo Pardini <ricardo@pardini.net>

The Radxa ROCK 5 ITX carries two on-board Realtek RTL8125 NICs behind
pcie2x1l1 and pcie2x1l2.

Describe the fixed function nodes and attach ethernet0/ethernet1
aliases, so that U-Boot's fdt_fixup_ethernet() can inject mac-address
properties from its ethaddr/eth1addr env, for stable MACs across
boots that both U-Boot and the kernel agree on.

Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
---
 arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
index 6f25e088f3189..f1d6647c57bf9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5-itx.dts
@@ -20,6 +20,8 @@ / {
 	compatible = "radxa,rock-5-itx", "rockchip,rk3588";
 
 	aliases {
+		ethernet0 = &rtl_eth0;
+		ethernet1 = &rtl_eth1;
 		mmc0 = &sdhci;
 		mmc1 = &sdmmc;
 		mmc2 = &sdio;
@@ -631,6 +633,20 @@ &pcie2x1l1 {
 	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_lan>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x300000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x30 0x3f>;
+
+		rtl_eth0: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x310000 0 0 0 0>;
+		};
+	};
 };
 
 /* RTL8125B_2 */
@@ -640,6 +656,20 @@ &pcie2x1l2 {
 	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_lan_phy2>;
 	status = "okay";
+
+	pcie@0,0 {
+		reg = <0x400000 0 0 0 0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges;
+		device_type = "pci";
+		bus-range = <0x40 0x4f>;
+
+		rtl_eth1: ethernet@0,0 {
+			compatible = "pci10ec,8125";
+			reg = <0x410000 0 0 0 0>;
+		};
+	};
 };
 
 &pcie30phy {

-- 
2.55.0

Re: [PATCH v5 2/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

[Diederik de Haas]

On Thu Sep 10, 2026 at 10:07 PM CEST, Ricardo Pardini via B4 Relay wrote:
> From: Ricardo Pardini <ricardo@pardini.net>
>
> The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs
> behind pcie2x1l0 and pcie2x1l2.
>
> Describe the fixed function nodes and attach ethernet0/ethernet1
> aliases, so that U-Boot's fdt_fixup_ethernet() can fill in the MAC
> from its ethaddr/eth1addr env. The on-NIC EEPROMs on this board are
> not pre-programmed with a unique MAC, so this gives a stable MAC
> across boots that both U-Boot and the kernel agree on.
>
> Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> index cfdb5c13f8606..550358a756618 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
> @@ -20,6 +20,8 @@ / {
>  	compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
>  
>  	aliases {
> +		ethernet0 = &rtl_eth0;
> +		ethernet1 = &rtl_eth1;
>  		mmc0 = &sdhci;
>  		mmc1 = &sdmmc;
>  	};
> @@ -644,6 +646,20 @@ &pcie2x1l0 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie2_0_rst>;

The new pinctrl reference is ``pcie_25glan_perstb_b_pin``, so this patch needs
to be rebased.

>  	status = "okay";
> +
> +	pcie@0,0 {
> +		reg = <0x200000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x21 0x2f>;
> +
> +		rtl_eth0: ethernet@0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x210000 0 0 0 0>;
> +		};

Described on page 23 of the schematic titled '2.5G Ethernet B' and ``U12``
(ie RTL8125BG) is connected to LAN2 which has ``ETH2`` as label on the case.

> +	};
>  };
>  
>  &pcie2x1l1 {
> @@ -660,6 +676,20 @@ &pcie2x1l2 {
>  	pinctrl-names = "default";
>  	pinctrl-0 = <&pcie2_2_rst>;

The new pinctrl reference is ``pcie_25glan_perstb_pin``.

>  	status = "okay";
> +
> +	pcie@0,0 {
> +		reg = <0x400000 0 0 0 0>;
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		ranges;
> +		device_type = "pci";
> +		bus-range = <0x41 0x4f>;
> +
> +		rtl_eth1: ethernet@0,0 {
> +			compatible = "pci10ec,8125";
> +			reg = <0x410000 0 0 0 0>;
> +		};

Described on page 22 of the schematic titled '2.5G Ethernet A' and ``U10``
(ie RTL8125BG) is connected to LAN1 which has ``ETH1`` as label on the case.

So this results in:
ETH1 -> rtl_eth1
ETH2 -> rtl_eth0

This sounds like a recipe for confusion and/or potential future mistakes.
I think using ``rtl_eth1`` and ``rtl_eth2`` would be less confusing, but
I'm fine with another construct which achieves a similar thing.

Cheers,
  Diederik

> +	};
>  };
>  
>  &pcie30phy {

Re: [PATCH v5 2/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

[Ricardo Pardini]

On 11/09/2026 11:52, Diederik de Haas wrote:
> On Thu Sep 10, 2026 at 10:07 PM CEST, Ricardo Pardini via B4 Relay wrote:
>> From: Ricardo Pardini <ricardo@pardini.net>
>>
>> The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs
>> behind pcie2x1l0 and pcie2x1l2.
>>
>> Describe the fixed function nodes and attach ethernet0/ethernet1
>> aliases, so that U-Boot's fdt_fixup_ethernet() can fill in the MAC
>> from its ethaddr/eth1addr env. The on-NIC EEPROMs on this board are
>> not pre-programmed with a unique MAC, so this gives a stable MAC
>> across boots that both U-Boot and the kernel agree on.
>>
>> Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
>> ---
>>   arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
>> index cfdb5c13f8606..550358a756618 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
>> @@ -20,6 +20,8 @@ / {
>>   	compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
>>   
>>   	aliases {
>> +		ethernet0 = &rtl_eth0;
>> +		ethernet1 = &rtl_eth1;
>>   		mmc0 = &sdhci;
>>   		mmc1 = &sdmmc;
>>   	};
>> @@ -644,6 +646,20 @@ &pcie2x1l0 {
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&pcie2_0_rst>;
> 
> The new pinctrl reference is ``pcie_25glan_perstb_b_pin``, so this patch needs
> to be rebased.

Indeed; I sent v5 vs v7.3-rc2 which doesn't have your recent series 
fixing those. I've rebased onto next-20260910 which does, will send in a 
v6 - but it's really just fuzz/context changes.

I'll wait a bit until Heiner/Krysztof/Heiko chime in ref the binding and 
its wording as that has been contentious in the previous versions. And 
who knows what Sashiko will find this time.

> 
>>   	status = "okay";
>> +
>> +	pcie@0,0 {
>> +		reg = <0x200000 0 0 0 0>;
>> +		#address-cells = <3>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +		device_type = "pci";
>> +		bus-range = <0x21 0x2f>;
>> +
>> +		rtl_eth0: ethernet@0,0 {
>> +			compatible = "pci10ec,8125";
>> +			reg = <0x210000 0 0 0 0>;
>> +		};
> 
> Described on page 23 of the schematic titled '2.5G Ethernet B' and ``U12``
> (ie RTL8125BG) is connected to LAN2 which has ``ETH2`` as label on the case.

Confirmed.

> 
>> +	};
>>   };
>>   
>>   &pcie2x1l1 {
>> @@ -660,6 +676,20 @@ &pcie2x1l2 {
>>   	pinctrl-names = "default";
>>   	pinctrl-0 = <&pcie2_2_rst>;
> 
> The new pinctrl reference is ``pcie_25glan_perstb_pin``.

Will also be fixed by rebasing onto linux-next.

> 
>>   	status = "okay";
>> +
>> +	pcie@0,0 {
>> +		reg = <0x400000 0 0 0 0>;
>> +		#address-cells = <3>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +		device_type = "pci";
>> +		bus-range = <0x41 0x4f>;
>> +
>> +		rtl_eth1: ethernet@0,0 {
>> +			compatible = "pci10ec,8125";
>> +			reg = <0x410000 0 0 0 0>;
>> +		};
> 
> Described on page 22 of the schematic titled '2.5G Ethernet A' and ``U10``
> (ie RTL8125BG) is connected to LAN1 which has ``ETH1`` as label on the case.
> 
> So this results in:
> ETH1 -> rtl_eth1
> ETH2 -> rtl_eth0
> 
> This sounds like a recipe for confusion and/or potential future mistakes.
> I think using ``rtl_eth1`` and ``rtl_eth2`` would be less confusing, but
> I'm fine with another construct which achieves a similar thing.

Yeah, that will result in aliases `ethernet0 = &rtl_eth1;` and 
`ethernet1 = &rtl_eth2;`. It could also be `rtl_lan1`/`rtl_lan2`, or as 
the schematics seems to to use the `_b` suffix, just `rtl_lan` and 
`rtl_lan_b`, I don't mind. Raise if you do, otherwise I'll send v6 as 
you suggested.

Userspace will be off-by-one vs the printed case labels, thus _some_ 
confusion will remain, but it's already better than the current 
enP2p33s0/enP4p65s0.

> 
> Cheers,
>    Diederik
> 
>> +	};
>>   };
>>   
>>   &pcie30phy {
> 

Thanks,
Ricardo

Re: [PATCH v5 2/7] arm64: dts: rockchip: describe PCIe RTL8125 Ethernet on NanoPC-T6

[Diederik de Haas]

On Fri Sep 11, 2026 at 2:19 PM CEST, Ricardo Pardini wrote:
> On 11/09/2026 11:52, Diederik de Haas wrote:
>> On Thu Sep 10, 2026 at 10:07 PM CEST, Ricardo Pardini via B4 Relay wrote:
>>> From: Ricardo Pardini <ricardo@pardini.net>
>>>
>>> The FriendlyElec NanoPC-T6 carries two on-board Realtek RTL8125 NICs
>>> behind pcie2x1l0 and pcie2x1l2.

Forgot to mention: thanks for this series :-)

>>> Describe the fixed function nodes and attach ethernet0/ethernet1
>>> aliases, so that U-Boot's fdt_fixup_ethernet() can fill in the MAC
>>> from its ethaddr/eth1addr env. The on-NIC EEPROMs on this board are
>>> not pre-programmed with a unique MAC, so this gives a stable MAC
>>> across boots that both U-Boot and the kernel agree on.
>>>
>>> Signed-off-by: Ricardo Pardini <ricardo@pardini.net>
>>> ---
>>>   arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi | 30 ++++++++++++++++++++++
>>>   1 file changed, 30 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
>>> index cfdb5c13f8606..550358a756618 100644
>>> --- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
>>> +++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
>>> @@ -20,6 +20,8 @@ / {
>>>   	compatible = "friendlyarm,nanopc-t6", "rockchip,rk3588";
>>>   
>>>   	aliases {
>>> +		ethernet0 = &rtl_eth0;
>>> +		ethernet1 = &rtl_eth1;
>>>   		mmc0 = &sdhci;
>>>   		mmc1 = &sdmmc;
>>>   	};
>>> @@ -644,6 +646,20 @@ &pcie2x1l0 {
>>>   	pinctrl-names = "default";
>>>   	pinctrl-0 = <&pcie2_0_rst>;
>> 
>> The new pinctrl reference is ``pcie_25glan_perstb_b_pin``, so this patch needs
>> to be rebased.
>
> Indeed; I sent v5 vs v7.3-rc2 which doesn't have your recent series 
> fixing those. I've rebased onto next-20260910 which does, will send in a 
> v6 - but it's really just fuzz/context changes.
>
> I'll wait a bit until Heiner/Krysztof/Heiko chime in ref the binding and 
> its wording as that has been contentious in the previous versions. And 
> who knows what Sashiko will find this time.

Agreed, their feedback is more important.

>>>   	status = "okay";
>>> +
>>> +	pcie@0,0 {
>>> +		reg = <0x200000 0 0 0 0>;
>>> +		#address-cells = <3>;
>>> +		#size-cells = <2>;
>>> +		ranges;
>>> +		device_type = "pci";
>>> +		bus-range = <0x21 0x2f>;
>>> +
>>> +		rtl_eth0: ethernet@0,0 {
>>> +			compatible = "pci10ec,8125";
>>> +			reg = <0x210000 0 0 0 0>;
>>> +		};
>> 
>> Described on page 23 of the schematic titled '2.5G Ethernet B' and ``U12``
>> (ie RTL8125BG) is connected to LAN2 which has ``ETH2`` as label on the case.
>
> Confirmed.
>
>> 
>>> +	};
>>>   };
>>>   
>>>   &pcie2x1l1 {
>>> @@ -660,6 +676,20 @@ &pcie2x1l2 {
>>>   	pinctrl-names = "default";
>>>   	pinctrl-0 = <&pcie2_2_rst>;
>> 
>> The new pinctrl reference is ``pcie_25glan_perstb_pin``.
>
> Will also be fixed by rebasing onto linux-next.
>
>> 
>>>   	status = "okay";
>>> +
>>> +	pcie@0,0 {
>>> +		reg = <0x400000 0 0 0 0>;
>>> +		#address-cells = <3>;
>>> +		#size-cells = <2>;
>>> +		ranges;
>>> +		device_type = "pci";
>>> +		bus-range = <0x41 0x4f>;
>>> +
>>> +		rtl_eth1: ethernet@0,0 {
>>> +			compatible = "pci10ec,8125";
>>> +			reg = <0x410000 0 0 0 0>;
>>> +		};
>> 
>> Described on page 22 of the schematic titled '2.5G Ethernet A' and ``U10``
>> (ie RTL8125BG) is connected to LAN1 which has ``ETH1`` as label on the case.
>> 
>> So this results in:
>> ETH1 -> rtl_eth1
>> ETH2 -> rtl_eth0
>> 
>> This sounds like a recipe for confusion and/or potential future mistakes.
>> I think using ``rtl_eth1`` and ``rtl_eth2`` would be less confusing, but
>> I'm fine with another construct which achieves a similar thing.
>
> Yeah, that will result in aliases `ethernet0 = &rtl_eth1;` and 
> `ethernet1 = &rtl_eth2;`. It could also be `rtl_lan1`/`rtl_lan2`, or as 
> the schematics seems to to use the `_b` suffix, just `rtl_lan` and 
> `rtl_lan_b`, I don't mind. Raise if you do, otherwise I'll send v6 as 
> you suggested.

I'm not a fan of the `_b` suffix (also not in the schematic; without an
`_a` suffix). Do the aliases have to be 0-based? If not, then `ethernet1`
and `ethernet2` would be my preferred solution. If it needs to be 0-based
then the off-by-one 'confusion' seems like the best solution.

> Userspace will be off-by-one vs the printed case labels, thus _some_ 
> confusion will remain, but it's already better than the current 
> enP2p33s0/enP4p65s0.

Indeed :-)
I triple checked whether my findings were correct before responding.

Thanks to your series, I had a look at NanoPi R5S and found a few issues.
There it's even worse:
PCB/schematic: LAN1=GbE and 'WAN' on the case; LAN2=2.5GbE and LAN1 on the
case; LAN3=2.5GbE and LAN2 on the case. 
And those result in `end0`, `enp1s0` and `enP1p17s0` respectively :-P

Cheers,
  Diederik

Re: [PATCH v5 1/7] dt-bindings: net: add Realtek RTL8125 PCIe Ethernet

[Heiko Stuebner]

Am Donnerstag, 10. September 2026, 22:07:51 Mitteleuropäische Sommerzeit schrieb Ricardo Pardini via B4 Relay:
> From: Ricardo Pardini <ricardo@pardini.net>
> 
> Add a binding for fixed/soldered Realtek RTL8125 PCIe Ethernet
> controller. As a PCIe device, its "pci10ec,8125" compatible is the
> Open Firmware spelling auto-derived from its PCI-SIG vendor/device IDs
> and is already covered by the generic dtschema pci-device.yaml. The
> compatible itself therefore needs no binding to be valid.
> 
> A dedicated binding is needed because board DTs describe these
> soldered function nodes in order to attach ethernet-controller
> properties to them: a placeholder local-mac-address that the bootloader
> fills in today, and potentially nvmem-cells, phy-handle, etc. in the
> future. This binding references ethernet-controller.yaml so those
> properties are validated on the RTL8125 PCI function nodes.
> 
> Suggested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> Signed-off-by: Ricardo Pardini <ricardo@pardini.net>

this needs to go through the network tree I think and their processes
are heavily automated, so this should be sent separately.

Heiko