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From: Radim Krcmar <rkrcmar@qti.qualcomm.com>
To: Guodong Xu <guodong.xu@oss.qualcomm.com>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: "linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
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	Paul Walmsley <paul.walmsley@sifive.com>,
	Conor Dooley <conor@kernel.org>,
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	"spacemit@lists.linux.dev" <spacemit@lists.linux.dev>,
	"sophgo@lists.linux.dev" <sophgo@lists.linux.dev>,
	"linux-kselftest@vger.kernel.org"
	<linux-kselftest@vger.kernel.org>,
	Andy Chiu <tchiu@tenstorrent.com>,
	Florian Weimer <fweimer@redhat.com>,
	Peter Bergner <bergner@oss.tenstorrent.com>,
	Zihong Yao <zihong.plct@isrc.iscas.ac.cn>,
	Mark Harris <mark.hsj@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Chen Wang <chen.wang@linux.dev>,
	Inochi Amaoto <inochiama@gmail.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v8 01/11] riscv: Add B to hwcap and hwprobe
Date: Tue, 29 Sep 2026 15:12:36 +0000	[thread overview]
Message-ID: <DLRWB8R7P6SF.1XIL0OXLZ2F23@qti.qualcomm.com> (raw)
In-Reply-To: <15151b8ab012ca7444d4117e393cf999.guodong.xu@oss.qualcomm.com>

2026-09-24T06:38:17-04:00, Guodong Xu <guodong.xu@oss.qualcomm.com>:
> On Mon, 21 Sep 2026 16:24:53 +0200, Heinrich Schuchardt wrote:
>> On 9/20/26 09:18, Guodong Xu wrote:
>>> [ ... ]
>>>   	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
>>>   	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
>>> +	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),
>>
>> Hello Guodong,
>>
>> The RISC-V Unpriviledged ISA specification has this description of 
>> extension B:
>>
>> "The B standard extension comprises instructions provided by the Zba, 
>> Zbb, and Zbs extensions."
>>
>> __RISCV_ISA_EXT_SUPERSET would imply that something else but 
>> riscv_b_exts is in B. But such an extra seems not to exist.
>>
>> So shouldn't __RISCV_ISA_EXT_BUNDLE be used here? Some code further 
>> change may be needed to set extension B if riscv_b_exts is fulfilled.
>
> Thanks for the review. Intentional, and the difference between the two
> macros is whether the extension gets a bit of its own.
>
> __RISCV_ISA_EXT_BUNDLE carries RISCV_ISA_EXT_INVALID as its id: parsing
> the name only sets the bits of its parts. That fits zk, zkn names, which
> are shorthands with no identity of their own beyond the ISA string.
>
> B is different: it is a single-letter standard extension with its own
> misa bit (in the same way as A), and AT_HWCAP on RISC-V is the bitmask
> of exactly those single letters, so the kernel needs a bit for B itself.
>
> A is declared the same way; with the spec defines A in the same words as
> B. If I can take that as a precedence.
>
> IMHO, "superset" in this table means "also sets these subset bits", not
> "contains something extra".

Zba, Zbb, and Zbs are equivalent to B for our purposes.

Are we sure that B will always be listed in the ISA string when Zba,
Zbb, and Zbs are present?

We could incorrectly lose RVA23U64 bit otherwise, and I think this was
Heinrich's concern as well...

(The "A" extension has the same issue...)

Thanks.

  reply	other threads:[~2026-09-29 15:13 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-20  7:18 [PATCH v8 00/11] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-09-20  7:18 ` [PATCH v8 01/11] riscv: Add B to hwcap and hwprobe Guodong Xu
2026-09-21 14:24   ` Heinrich Schuchardt
2026-09-24 10:38     ` Guodong Xu
2026-09-29 15:12       ` Radim Krcmar [this message]
2026-09-29 16:30         ` Heinrich Schuchardt
2026-09-29 19:24           ` Conor Dooley
2026-09-20  7:18 ` [PATCH v8 02/11] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-09-20  7:18 ` [PATCH v8 03/11] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-09-20  7:18 ` [PATCH v8 04/11] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-09-20  7:18 ` [PATCH v8 05/11] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-09-20  7:18 ` [PATCH v8 06/11] riscv: dts: spacemit: k1: " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 07/11] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 08/11] riscv: Add a getter for user PMLEN support Guodong Xu
2026-09-20  7:18 ` [PATCH v8 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-09-20  7:18 ` [PATCH v8 10/11] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-09-20  7:18 ` [PATCH v8 11/11] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-09-29 16:00   ` Radim Krcmar

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