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From: Conor Dooley <conor@kernel.org>
To: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Cc: Radim Krcmar <rkrcmar@qti.qualcomm.com>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"spacemit@lists.linux.dev" <spacemit@lists.linux.dev>,
	"sophgo@lists.linux.dev" <sophgo@lists.linux.dev>,
	"linux-kselftest@vger.kernel.org"
	<linux-kselftest@vger.kernel.org>,
	Andy Chiu <tchiu@tenstorrent.com>,
	Florian Weimer <fweimer@redhat.com>,
	Peter Bergner <bergner@oss.tenstorrent.com>,
	Zihong Yao <zihong.plct@isrc.iscas.ac.cn>,
	Mark Harris <mark.hsj@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	Conor Dooley <conor.dooley@microchip.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Chen Wang <chen.wang@linux.dev>,
	Inochi Amaoto <inochiama@gmail.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>,
	Guodong Xu <guodong.xu@oss.qualcomm.com>
Subject: Re: [PATCH v8 01/11] riscv: Add B to hwcap and hwprobe
Date: Tue, 29 Sep 2026 20:24:15 +0100	[thread overview]
Message-ID: <20260929-operative-anointer-7f54be845b54@spud> (raw)
In-Reply-To: <70a3451c-db31-41d0-af9d-8c9e123557f6@canonical.com>

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On Tue, Sep 29, 2026 at 06:30:49PM +0200, Heinrich Schuchardt wrote:
> On 9/29/26 17:12, Radim Krcmar wrote:
> > 2026-09-24T06:38:17-04:00, Guodong Xu <guodong.xu@oss.qualcomm.com>:
> > > On Mon, 21 Sep 2026 16:24:53 +0200, Heinrich Schuchardt wrote:
> > > > On 9/20/26 09:18, Guodong Xu wrote:
> > > > > [ ... ]
> > > > >    	__RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_Q),
> > > > >    	__RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_C, riscv_c_exts),
> > > > > +	__RISCV_ISA_EXT_SUPERSET(b, RISCV_ISA_EXT_B, riscv_b_exts),
> > > > 
> > > > Hello Guodong,
> > > > 
> > > > The RISC-V Unpriviledged ISA specification has this description of
> > > > extension B:
> > > > 
> > > > "The B standard extension comprises instructions provided by the Zba,
> > > > Zbb, and Zbs extensions."
> > > > 
> > > > __RISCV_ISA_EXT_SUPERSET would imply that something else but
> > > > riscv_b_exts is in B. But such an extra seems not to exist.
> > > > 
> > > > So shouldn't __RISCV_ISA_EXT_BUNDLE be used here? Some code further
> > > > change may be needed to set extension B if riscv_b_exts is fulfilled.
> > > 
> > > Thanks for the review. Intentional, and the difference between the two
> > > macros is whether the extension gets a bit of its own.
> > > 
> > > __RISCV_ISA_EXT_BUNDLE carries RISCV_ISA_EXT_INVALID as its id: parsing
> > > the name only sets the bits of its parts. That fits zk, zkn names, which
> > > are shorthands with no identity of their own beyond the ISA string.
> > > 
> > > B is different: it is a single-letter standard extension with its own
> > > misa bit (in the same way as A), and AT_HWCAP on RISC-V is the bitmask
> > > of exactly those single letters, so the kernel needs a bit for B itself.
> > > 
> > > A is declared the same way; with the spec defines A in the same words as
> > > B. If I can take that as a precedence.
> > > 
> > > IMHO, "superset" in this table means "also sets these subset bits", not
> > > "contains something extra".
> > 
> > Zba, Zbb, and Zbs are equivalent to B for our purposes.
> > 
> > Are we sure that B will always be listed in the ISA string when Zba,
> > Zbb, and Zbs are present?
> > 
> > We could incorrectly lose RVA23U64 bit otherwise, and I think this was
> > Heinrich's concern as well...
> > 
> > (The "A" extension has the same issue...)
> > 
> > Thanks.
> 
> If Zba, Zbb, and Zbs are present the kernel should set the B flag in
> hwprobe. This is why RISCV_ISA_EXT_SUPERSET() cannot be used to describe the
> B extension. RISCV_ISA_EXT_BUNDLE looks more appropriate but may lack
> functionality.
> 
> RVA23U64 looks like an RISCV_ISA_EXT_BUNDLE() to me, too.
> 
> Unfortunately these macros are not properly documented.
> 
> It would be helpful to first align on the meaning and usage of the macros
> and document them properly.

The intended meaning was "bundle contains no additional features beyond
the components" and "superset contains additional features beyond the
components".

IIRC the reason for differentiation between the two was to simplify
things in the kernel and avoid having code which requires y feature checking
for "bundle extension xyz", because firmware might only set "component
extension y" and therefore get a false negative on support.
Probably ditto for userspace parsing /proc/cpuinfo, since I don't think
hwprobe existed at that point. The things that are using superset now
don't quite match that, because some extensions have been retroactively
changed by RVI to match the bundle definition (due to new extensions being
created for subsets of an existing extension) and superset was used also for
the xlinuxenvcfg stuff.

At this point, I think we could probably just cull the differentiation
entirely, retaining a macro called "bundle" that has the behaviour of
the current "superset". People should just know to check the minimum
required extension (that's common sense surely?!?) and the kernel will
always propagate support down to components. This is at least the 3rd
time recently that I have seen confusion over what each is supposed to
do.


> 
> ---
> 
> The benefit of an additional hwprobe flags for B is limited. When I want to
> check for B I can already use:
> 
> RISCV_HWPROBE_EXT_B =
> RISCV_HWPROBE_EXT_ZBA | RISCV_HWPROBE_EXT_ZBB | RISCV_HWPROBE_EXT_ZBS;
> 
> if ((value & RISCV_HWPROBE_EXT_B) == RISCV_HWPROBE_EXT_B) {
> 	// Hurray, I have the B extension.
> }
> 
> There is more utility in the RVA23U64 flag because it combines values from
> RISCV_HWPROBE_KEY_BASE_BEHAVIOR, RISCV_HWPROBE_KEY_IMA_EXT_0, and
> RISCV_HWPROBE_KEY_IMA_EXT_1.
> 
> Best regards
> 
> Heinrich

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  reply	other threads:[~2026-09-29 19:24 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-20  7:18 [PATCH v8 00/11] riscv: hwprobe: Expose RVA23U64 base behavior Guodong Xu
2026-09-20  7:18 ` [PATCH v8 01/11] riscv: Add B to hwcap and hwprobe Guodong Xu
2026-09-21 14:24   ` Heinrich Schuchardt
2026-09-24 10:38     ` Guodong Xu
2026-09-29 15:12       ` Radim Krcmar
2026-09-29 16:30         ` Heinrich Schuchardt
2026-09-29 19:24           ` Conor Dooley [this message]
2026-09-20  7:18 ` [PATCH v8 02/11] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-09-20  7:18 ` [PATCH v8 03/11] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-09-20  7:18 ` [PATCH v8 04/11] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-09-20  7:18 ` [PATCH v8 05/11] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-09-20  7:18 ` [PATCH v8 06/11] riscv: dts: spacemit: k1: " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 07/11] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 08/11] riscv: Add a getter for user PMLEN support Guodong Xu
2026-09-20  7:18 ` [PATCH v8 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-09-20  7:18 ` [PATCH v8 10/11] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-09-20  7:18 ` [PATCH v8 11/11] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-09-29 16:00   ` Radim Krcmar

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