From: "Danilo Krummrich" <dakr@kernel.org>
To: "Zhi Wang" <zhiw@nvidia.com>
Cc: rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, aliceryhl@google.com,
bhelgaas@google.com, kwilczynski@kernel.org, ojeda@kernel.org,
boqun@kernel.org, gary@garyguo.net, bjorn3_gh@protonmail.com,
lossin@kernel.org, a.hindborg@kernel.org, tmgross@umich.edu,
markus.probst@posteo.de, cjia@nvidia.com, smitra@nvidia.com,
ankita@nvidia.com, aniketa@nvidia.com, kwankhede@nvidia.com,
targupta@nvidia.com, kjaju@nvidia.com, alkumar@nvidia.com,
acourbot@nvidia.com, jhubbard@nvidia.com, zhiwang@kernel.org,
"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: Re: [PATCH v10 1/1] rust: pci: add extended capability and SR-IOV support
Date: Wed, 30 Sep 2026 22:34:27 +0200 [thread overview]
Message-ID: <DLSXS9MO4YW5.2YLITM1OJ7P0P@kernel.org> (raw)
In-Reply-To: <20260906060404.3336193-2-zhiw@nvidia.com>
On Sun Sep 6, 2026 at 8:04 AM CEST, Zhi Wang wrote:
> + pub fn vf_bars(&self) -> Result<impl Iterator<Item = ExtSriovVfBar>> {
> + let slots: [u32; NUM_VF_BARS] =
> + core::array::from_fn(|slot| crate::io_read!(*self, .vf_bar[panic: slot]));
> + let mut slots = slots.into_iter();
> + let mut bars = [None; NUM_VF_BARS];
> + let mut count = 0;
> +
> + let mut decode = || {
> + while let Some(low) = slots.next().map(BarLow::from) {
> + // SR-IOV VF BARs describe memory-space apertures; an I/O-space encoding is not
> + // valid for these registers.
> + if low.io_space() {
> + return Err(EINVAL);
> + }
> +
> + let low_address = u64::from(low.address()) << BarLow::ADDRESS_SHIFT;
> + let bar = match low.memory_type()? {
> + BarMemoryType::Bits64 => ExtSriovVfBar {
> + address: (u64::from(slots.next().ok_or(EINVAL)?) << 32) | low_address,
> + is_64bit: true,
> + },
> + BarMemoryType::Bits32 => ExtSriovVfBar {
> + address: low_address,
> + is_64bit: false,
> + },
> + };
> +
> + bars[count] = Some(bar);
> + count += 1;
> + }
> +
> + Ok(())
> + };
> +
> + decode().inspect_err(|_| {
> + dev_err!(self.pdev, "invalid VF BAR encoding in SR-IOV capability\n");
> + })?;
> + Ok(bars.into_iter().flatten())
> + }
I don't mind too much, but can you please remind me why we decode the VF BAR
registers and can't use the PCI core's VF resource information instead?
(I gave it a very quick try and using pci_bus_address() and pci_resource_flags()
actually turned out worse, but that could be me spending less than 5 minutes on
it. :)
prev parent reply other threads:[~2026-09-30 20:34 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-06 6:04 [PATCH v10 0/1] Rust PCI capability infrastructure " Zhi Wang
2026-09-06 6:04 ` [PATCH v10 1/1] rust: pci: add extended capability " Zhi Wang
2026-09-30 20:34 ` Danilo Krummrich [this message]
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