From: "Junhui Liu" <junhui.liu@pigmoral.tech>
To: "Vinicius Pedrosa" <vinicius.eduardo.pedrosa@gmail.com>,
"Junhui Liu" <junhui.liu@pigmoral.tech>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Chen-Yu Tsai" <wens@kernel.org>,
"Jernej Skrabec" <jernej.skrabec@gmail.com>,
"Samuel Holland" <samuel@sholland.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>,
"Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Richard Cochran" <richardcochran@gmail.com>
Cc: <linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-sunxi@lists.linux.dev>, <linux-kernel@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <netdev@vger.kernel.org>,
"Jerome Brunet" <jbrunet@baylibre.com>,
"Enzo Adriano" <enzo.adriano.code@gmail.com>,
"Andre Przywara" <andre.przywara@arm.com>,
"Norman Herms" <dockseed@proton.me>
Subject: Re: [PATCH v5 3/8] clk: sunxi-ng: a733: Add PRCM CCU
Date: Wed, 07 Oct 2026 11:34:49 +0800 [thread overview]
Message-ID: <DLYAHDTH3129.3AYF0OSHL8RJ8@pigmoral.tech> (raw)
In-Reply-To: <20261005183038.417798-1-vinicius.eduardo.pedrosa@gmail.com>
Hi Vinicius,
Thanks for testing.
On Tue Oct 6, 2026 at 2:30 AM CST, Vinicius Pedrosa wrote:
> Hi Junhui,
>
> On Wed Sep 30, 2026 at 1:26 AM CST, Junhui Liu wrote:
>> +static SUNXI_CCU_GATE_HW(bus_r_msgbox_clk, "bus-r-msgbox", &r_ahb_clk.common.hw, 0x17c, BIT(0), 0);
>
> [...]
>
>> +static SUNXI_CCU_GATE_HW(bus_r_riscv_clk, "bus-r-riscv", &r_apb0_clk.common.hw,
>> + 0x21c, BIT(0), 0);
>
> I'm bringing up mainline on a Radxa Cubie A7Z (PCB V1.11, 1 GiB). With
> 7.3-rc6, this series and a local common-DT integration, PSCI reboot and
> power-off hang once unused clocks are disabled. The boot chain uses
> vendor boot0/BL31 and source-built SCP/U-Boot.
>
> Keeping both of these gates enabled fixes reboot; either alone still
> hangs. With only these two marked CLK_IS_CRITICAL, reboot returns to
> boot0 and power-off drops DCDC1 from 3.3 V to 0.7 V and turns off the
> green LED with power still connected. I haven't checked whether each
> gate is needed for power-off on its own.
>
> My guess is that BL31 talks to the SCP for these, but I haven't traced
> it, and it may be specific to the vendor firmware.
Yes, it appears that the vendor SCP firmware runs on the E902 core
instead of the ARISC OR100 core on the A733. Disabling either
bus-r-riscv or bus-r-msgbox breaks the SCPI communication path between
TF-A and the SCP firmware.
>
> Would it make sense to mark them CLK_IS_CRITICAL, like bus-r-cpucfg
> already is? I can test the next revision on this board either way.
Mainline TF-A uses native PSCI for reboot and power-off on the NCAT2
family. Even if Crust is ported to the A733 in the future, I would
expect it to run on the ARISC OR100 core rather than the E902 core.
(Also see discussion in [1].)
The E902 may also be supported by the Linux remoteproc and mailbox
drivers in the future. In that case, bus-r-riscv and bus-r-msgbox
should be managed by their respective drivers instead of being kept
enabled globally.
I don't know if marking these clocks as CLK_IS_CRITICAL just for the
vendor SCP firmware is a good idea...
[1] https://lore.kernel.org/linux-sunxi/556cd32394062960a3ea4af0011155cfa83ae91f.camel@d-silva.org/T/#u
>
> Thanks,
> Vinicius
--
Best regards,
Junhui Liu
next prev parent reply other threads:[~2026-10-07 3:35 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 17:26 [PATCH v5 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Junhui Liu
2026-09-29 17:26 ` [PATCH v5 1/8] dt-bindings: clk: sun60i-a733-ccu: Add Allwinner A733 support Junhui Liu
2026-09-29 17:26 ` [PATCH v5 2/8] clk: sunxi-ng: sdm: Add dual patterns support Junhui Liu
2026-09-29 17:26 ` [PATCH v5 3/8] clk: sunxi-ng: a733: Add PRCM CCU Junhui Liu
2026-10-03 14:00 ` Chen-Yu Tsai
2026-10-03 14:57 ` Junhui Liu
2026-10-03 16:51 ` Norman Herms
2026-10-03 14:57 ` Norman Herms
2026-10-05 18:30 ` Vinicius Pedrosa
2026-10-07 3:34 ` Junhui Liu [this message]
2026-09-29 17:26 ` [PATCH v5 4/8] clk: sunxi-ng: a733: Add PLL clocks support Junhui Liu
2026-10-04 10:08 ` Chen-Yu Tsai
2026-09-29 17:26 ` [PATCH v5 5/8] clk: sunxi-ng: a733: Add bus " Junhui Liu
2026-10-04 10:20 ` Chen-Yu Tsai
2026-09-29 17:26 ` [PATCH v5 6/8] clk: sunxi-ng: a733: Add mod " Junhui Liu
2026-09-29 17:26 ` [PATCH v5 7/8] clk: sunxi-ng: a733: Add bus clock gates Junhui Liu
2026-10-04 11:03 ` Chen-Yu Tsai
2026-10-04 11:14 ` AW: " Norman Herms
2026-10-05 4:41 ` Junhui Liu
2026-10-05 9:17 ` Andre Przywara
2026-10-06 14:50 ` Junhui Liu
2026-10-06 15:29 ` Andre Przywara
2026-10-06 15:59 ` Junhui Liu
2026-09-29 17:26 ` [PATCH v5 8/8] clk: sunxi-ng: a733: Add reset lines Junhui Liu
2026-10-04 11:04 ` Chen-Yu Tsai
2026-10-03 12:52 ` [PATCH v5 0/8] clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM Junhui Liu
2026-10-03 13:37 ` Chen-Yu Tsai
2026-10-03 13:51 ` Norman Herms
2026-10-03 14:35 ` Junhui Liu
2026-10-03 15:05 ` Norman Herms
2026-10-03 15:23 ` Junhui Liu
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