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From: "Hawkins, Nick" <nick.hawkins@hpe.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: "Verdun, Jean-Marie" <verdun@hpe.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"krzysztof.kozlowski+dt@linaro.org" 
	<krzysztof.kozlowski+dt@linaro.org>,
	"linux@armlinux.org.uk" <linux@armlinux.org.uk>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH v1 1/5] soc: hpe: add support for HPE GXP Programmable Register Driver
Date: Wed, 12 Oct 2022 20:25:00 +0000	[thread overview]
Message-ID: <DM4PR84MB19276978EB630CF08833E5A488229@DM4PR84MB1927.NAMPRD84.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <c6ab6116-5d92-132e-48fc-b731fd244d72@linaro.org>

Greetings Krysztof,

Thanks for the feedback! I have several questions below:

> > +
> > +static ssize_t server_id_show(struct device *dev, struct 
> > +device_attribute *attr, char *buf) {
> > +	struct gxp_plreg_drvdata *drvdata = dev_get_drvdata(dev);
> > +	int value_upper;
> > +	int value_lower;
> > +	ssize_t ret;
> > +	u32 trans_offset;
> > +	u32 trans_shift;
> > +
> > +	/* read upper first */
> > +	address_translation(drvdata->server_id.upper[BYTE],
> > +			    &trans_offset,
> > +			    &trans_shift);
> > +	regmap_read(drvdata->plreg_map, trans_offset, &value_upper);
> > +	value_upper = value_upper >> trans_shift;
> > +	value_upper = value_upper & drvdata->server_id.upper[MASK];
> > +
> > +	/* read lower last */
> > +	address_translation(drvdata->server_id.lower[BYTE],
> > +			    &trans_offset,
> > +			    &trans_shift);
> > +	regmap_read(drvdata->plreg_map, trans_offset, &value_lower);
> > +	value_lower = value_lower >> trans_shift;
> > +	value_lower = value_lower & drvdata->server_id.lower[MASK];
> > +
> > +	ret = sprintf(buf, "0x%04x", value_upper | value_lower);
> > +
> > +	return ret;
> > +}
> > +
> > +static DEVICE_ATTR_RO(server_id);

> Missing sysfs documentation.

Can you point me at the proper location / documentation for documenting sysfs? Thanks!

> > +	for (i = 0; i <= MASK; i++) {
> > +		if (of_property_read_u32_index(np, "grp5", i,
> > +					       &drvdata->grp_intr_flags.grp5[i])) {
> > +			dev_err(&pdev->dev,
> > +				"grp5intsflags is missing its 'grp5' property index %d\n", i);
> > +			return -ENODEV;
> > +		}
> > +	}
> > +
> > +	np = of_get_child_by_name(pdev->dev.of_node, "pwrbtn");
> > +	if (!np) {
> > +		dev_err(&pdev->dev, "%pOF is missing its 'pwrbtn' node\n", np);
> > +		return -ENODEV;
> > +	}
> > +
> > +	for (i = 0; i <= VALUE; i++) {
> > +		if (of_property_read_u32_index(np, "latch", i, 
> > +&drvdata->pwrbtn.latch[i])) {

> Undocumented properties. NAK.

If each child node of hpe,gxp-plreg were documented with their respective properties would this be acceptable?

Such as:
Fan-1 {
	Compatible="hpe,gxp-plreg-fan";
	id = <0x27>;
	bit = <0x01>;
	fail = <0x24>;
	inst = <0x22>;
};
	

> > +			dev_err(&pdev->dev, "pwrbtn is missing its 'latch' property index %d\n", i);
> > +			return -ENODEV;
> > +		}
> > +	}
> > +
> > +	drvdata->gpio_chip = plreg_chip;
> > +	drvdata->gpio_chip.ngpio = 100;
> > +	drvdata->gpio_chip.parent = &pdev->dev;
> > +
> > +	girq = &drvdata->gpio_chip.irq;
> > +	girq->chip = &gxp_gpio_irqchip;
> > +	/* This will let us handle the parent IRQ in the driver */
> > +	girq->parent_handler = NULL;
> > +	girq->num_parents = 0;
> > +	girq->parents = NULL;
> > +	girq->default_type = IRQ_TYPE_NONE;
> > +	girq->handler = handle_edge_irq;
> > +	/* Set up interrupt from PLREG Group 5 Mask */

> Please read Linux coding style. There is a chapter about size of functions. Read it. Actually, read the rest as well... It's ok if
probe() grows above our limit, but this is huge. Really too big.

I will do this and work on breaking up this code into smaller functions.

Thanks,

-Nick Hawkins

  reply	other threads:[~2022-10-12 20:25 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-11 18:55 [PATCH v1 0/5] Add PLREG and SPI Driver GXP Support nick.hawkins
2022-10-11 18:55 ` [PATCH v1 1/5] soc: hpe: add support for HPE GXP Programmable Register Driver nick.hawkins
2022-10-11 20:05   ` Krzysztof Kozlowski
2022-10-12 20:25     ` Hawkins, Nick [this message]
2022-10-13 12:27       ` Krzysztof Kozlowski
2022-10-12  0:28   ` kernel test robot
2022-10-11 18:55 ` [PATCH v1 2/5] dt-bindings: soc: hpe: Add hpe,gxp-plreg nick.hawkins
2022-10-11 19:51   ` Krzysztof Kozlowski
2022-10-11 20:27   ` Rob Herring
2022-10-12 19:56     ` Hawkins, Nick
2022-10-22 15:52       ` Krzysztof Kozlowski
2022-10-25  0:03         ` Hawkins, Nick
2022-10-25  0:15           ` Krzysztof Kozlowski
2022-10-25 18:44             ` Hawkins, Nick
2022-10-25 18:55               ` Krzysztof Kozlowski
2022-10-25 19:26                 ` Hawkins, Nick
2022-10-25 19:33                   ` Krzysztof Kozlowski
     [not found]                     ` <DM4PR84MB197662C12018090C312AF72DD6319@DM4PR84MB1976.NAMPRD84.PROD.OUTLOOK.COM>
2022-10-25 19:48                       ` Krzysztof Kozlowski
2022-10-25 19:49                       ` Krzysztof Kozlowski
2022-10-11 18:55 ` [PATCH v1 3/5] ARM: dts: hpe: Add PLREG/SPI Support nick.hawkins
2022-10-11 19:53   ` Krzysztof Kozlowski
2022-10-11 18:55 ` [PATCH v1 4/5] ARM: multi_v7_defconfig: Enable GXP SPI and PLREG Drivers nick.hawkins
2022-10-11 19:54   ` Krzysztof Kozlowski
2022-10-11 18:55 ` [PATCH v1 5/5] MAINTAINERS: Add HPE SOC Drivers nick.hawkins
2022-10-11 20:06   ` Krzysztof Kozlowski

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