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* bios disables second cpu
@ 2001-10-25  1:12 Anton Petrusevich
  2001-10-25  2:20 ` Martin J. Bligh
  0 siblings, 1 reply; 2+ messages in thread
From: Anton Petrusevich @ 2001-10-25  1:12 UTC (permalink / raw)
  To: linux-kernel

Hi,

Something strange is going on. The server in question is dual P-III/850 on
Intel 440GX+ board. Neither 2.4 nor 2.2 kernel doesn't see second cpu, but some
APIC error. What's the problem? Here dmesg goes:

Linux version 2.4.12-ac6 (root@bugs2k) (gcc version 2.95.4 20011006 (Debian prer
elease)) #2 SMP Thu Oct 25 08:15:00 UTC 2001
BIOS-provided physical RAM map:
 BIOS-e820: 0000000000000000 - 000000000009f400 (usable)
 BIOS-e820: 000000000009f400 - 00000000000a0000 (reserved)
 BIOS-e820: 00000000000e8000 - 0000000000100000 (reserved)
 BIOS-e820: 0000000000100000 - 000000005fff0000 (usable)
 BIOS-e820: 000000005fff0000 - 000000005ffffc00 (ACPI data)
 BIOS-e820: 000000005ffffc00 - 0000000060000000 (ACPI NVS)
 BIOS-e820: 00000000fec00000 - 00000000fec10000 (reserved)
 BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
 BIOS-e820: 00000000fff80000 - 0000000100000000 (reserved)
639MB HIGHMEM available.
found SMP MP-table at 000f6ab0
hm, page 000f6000 reserved twice.
hm, page 000f7000 reserved twice.
hm, page 0009f000 reserved twice.
hm, page 000a0000 reserved twice.
On node 0 totalpages: 393200
zone(0): 4096 pages.
zone(1): 225280 pages.
zone(2): 163824 pages.
Intel MultiProcessor Specification v1.1
    Virtual Wire compatibility mode.
OEM ID: INTEL    Product ID: Lancewood    APIC at: 0xFEE00000
Processor #0 Pentium(tm) Pro APIC version 17
I/O APIC #1 Version 17 at 0xFEC00000.
Processors: 1
Kernel command line: auto BOOT_IMAGE=Linux ro root=801
Initializing CPU#0
Detected 846.342 MHz processor.
Console: colour VGA+ 80x25
Calibrating delay loop... 1690.82 BogoMIPS
Memory: 1544072k/1572800k available (1155k kernel code, 28340k reserved, 380k da
ta, 220k init, 655296k highmem)
Dentry-cache hash table entries: 262144 (order: 9, 2097152 bytes)
Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
Buffer-cache hash table entries: 131072 (order: 7, 524288 bytes)
Page-cache hash table entries: 524288 (order: 9, 2097152 bytes)
CPU: Before vendor init, caps: 0387fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 256K
CPU: After vendor init, caps: 0387fbff 00000000 00000000 00000000
CPU serial number disabled.
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU:     After generic, caps: 0383fbff 00000000 00000000 00000000
CPU:             Common caps: 0383fbff 00000000 00000000 00000000
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch@atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: Before vendor init, caps: 0383fbff 00000000 00000000, vendor = 0
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 256K
CPU: After vendor init, caps: 0383fbff 00000000 00000000 00000000
Intel machine check reporting enabled on CPU#0.
CPU:     After generic, caps: 0383fbff 00000000 00000000 00000000
CPU:             Common caps: 0383fbff 00000000 00000000 00000000
CPU0: Intel Pentium III (Coppermine) stepping 06
per-CPU timeslice cutoff: 731.27 usecs.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Error: only one processor found.
ENABLING IO-APIC IRQs
Setting 1 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 1 ... ok.
init IO_APIC IRQs
 IO-APIC (apicid-pin) 1-0, 1-16, 1-17, 1-18, 1-19, 1-20, 1-21, 1-22, 1-23 not co
nnected.
..TIMER: vector=0x31 pin1=2 pin2=0
number of MP IRQ sources: 16.
number of IO-APIC #1 registers: 24.
testing the IO APIC.......................

IO APIC #1......
.... register #00: 01000000
.......    : physical APIC id: 01
.... register #01: 00170011
.......     : max redirection entries: 0017
.......     : PRQ implemented: 0
.......     : IO APIC version: 0011
.... register #02: 00000000
.......     : arbitration: 00
.... IRQ redirection table:
 NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
 00 000 00  1    0    0   0   0    0    0    00
 01 001 01  0    0    0   0   0    1    1    39
 02 001 01  0    0    0   0   0    1    1    31
 03 001 01  0    0    0   0   0    1    1    41
 04 001 01  0    0    0   0   0    1    1    49
 05 001 01  0    0    0   0   0    1    1    51
 06 001 01  0    0    0   0   0    1    1    59
 07 001 01  0    0    0   0   0    1    1    61
 08 001 01  0    0    0   0   0    1    1    69
 09 001 01  1    1    0   0   0    1    1    71
 0a 001 01  1    1    0   0   0    1    1    79
 0b 001 01  1    1    0   0   0    1    1    81
 0c 001 01  0    0    0   0   0    1    1    89
 0d 001 01  0    0    0   0   0    1    1    91
 0e 001 01  0    0    0   0   0    1    1    99
 0f 001 01  0    0    0   0   0    1    1    A1
 10 000 00  1    0    0   0   0    0    0    00
 11 000 00  1    0    0   0   0    0    0    00
 12 000 00  1    0    0   0   0    0    0    00
 13 000 00  1    0    0   0   0    0    0    00
 14 000 00  1    0    0   0   0    0    0    00
 15 000 00  1    0    0   0   0    0    0    00
 16 000 00  1    0    0   0   0    0    0    00
 17 000 00  1    0    0   0   0    0    0    00
IRQ to pin mappings:
IRQ0 -> 0:2
IRQ1 -> 0:1
IRQ3 -> 0:3
IRQ4 -> 0:4
IRQ5 -> 0:5
IRQ6 -> 0:6
IRQ7 -> 0:7
IRQ8 -> 0:8
IRQ9 -> 0:9
IRQ10 -> 0:10
IRQ11 -> 0:11
IRQ12 -> 0:12
IRQ13 -> 0:13
IRQ14 -> 0:14
IRQ15 -> 0:15
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 846.3795 MHz.
..... host bus clock speed is 99.5739 MHz.
cpu: 0, clocks: 995739, slice: 497869
CPU0<T0:995728,T1:497856,D:3,S:497869,C:995739>
Waiting on wait_init_idle (map = 0x0)
All processors have done init_idle

[and so on]

Best regards,
-- 
Anton Petrusevich


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: bios disables second cpu
  2001-10-25  1:12 bios disables second cpu Anton Petrusevich
@ 2001-10-25  2:20 ` Martin J. Bligh
  0 siblings, 0 replies; 2+ messages in thread
From: Martin J. Bligh @ 2001-10-25  2:20 UTC (permalink / raw)
  To: Anton Petrusevich, linux-kernel

> Something strange is going on. The server in question is dual P-III/850 on
> Intel 440GX+ board. Neither 2.4 nor 2.2 kernel doesn't see second cpu, but some
> APIC error. What's the problem? Here dmesg goes:
...
> Intel MultiProcessor Specification v1.1
>     Virtual Wire compatibility mode.
> OEM ID: INTEL    Product ID: Lancewood    APIC at: 0xFEE00000
> Processor #0 Pentium(tm) Pro APIC version 17
> I/O APIC #1 Version 17 at 0xFEC00000.
> Processors: 1

Looks like your MPS table is lacking. What happens if you do 
"phys_cpu_present_map = 3" at the end of smp_read_mpc() 
in arch/i386/kernel/mpparse.c ?

Martin.


^ permalink raw reply	[flat|nested] 2+ messages in thread

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2001-10-25  1:12 bios disables second cpu Anton Petrusevich
2001-10-25  2:20 ` Martin J. Bligh

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