From: Johannes Weiner <jw@emlix.com>
To: Chris Zankel <chris@zankel.net>
Cc: linux-kernel@vger.kernel.org
Subject: [patch] xtensa: enforce slab alignment to maximum register width
Date: Wed, 4 Mar 2009 14:56:18 +0100 [thread overview]
Message-ID: <E1LerZg-0000Rp-AX@mailer.emlix.com> (raw)
From: Oskar Schirmer <os@emlix.com>
XCHAL_DATA_WIDTH is the maximum register width, slab caches should be
aligned to this.
Theoretical fix as all variants have had an XCHAL_DATA_WIDTH of 4
(wordsize) for now. But the S6000 variant will raise this to 16.
Signed-off-by: Oskar Schirmer <os@emlix.com>
Signed-off-by: Johannes Weiner <jw@emlix.com>
---
arch/xtensa/include/asm/processor.h | 2 ++
1 file changed, 2 insertions(+)
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -25,6 +25,8 @@
# error Linux requires the Xtensa Windowed Registers Option.
#endif
+#define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH
+
/*
* User space process size: 1 GB.
* Windowed call ABI requires caller and callee to be located within the same
next reply other threads:[~2009-03-04 13:56 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-04 13:56 Johannes Weiner [this message]
2009-03-04 14:32 ` Pekka Enberg
2009-03-04 21:33 ` [PATCH] nand_bbt.c, kernel 2.6.28.7 Basterash, Tom
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