mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
* Fwd: PTE question
@ 2002-09-20 20:09 Mehdi Hashemian
  0 siblings, 0 replies; 2+ messages in thread
From: Mehdi Hashemian @ 2002-09-20 20:09 UTC (permalink / raw)
  To: linux-kernel

Hello,

As I did not receive any response for the following question, I appreciate 
if someone guide me to the right email list to post this question, if there 
is any.

Appreciate it,
Mehdi

----Original Message Follows----
From: "Mehdi Hashemian" <mhashemian@hotmail.com>
To: linux-kernel@vger.kernel.org
Subject: PTE question
Date: Wed, 18 Sep 2002 18:52:25 -0700

Hello,

Appreciate if someone checks this piece of code. I try to diable cache and 
write-through bits in PTE but somehow PTE address is within first 16MB of 
memory (DMA_ZONE) and later when Kernel tries to allocate more pages, it 
chooses the same address range and this piece of code corrupts memory by 
ORing these bits. Any help appreciated!

    {
        addr = __get_dma_pages(priority, order);

        int npages = __get_npages(order);
	unsigned long addr2 = addr;
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte;
	int i;

	for (i = 0; i < npages; i++)
	{
	    pgd = pgd_offset(&init_mm, addr2);
	    pmd = pmd_offset(pgd, addr2);
	    pte = pte_offset(pmd, addr2);
	    pte_val(*pte) |= (_PAGE_PCD | _PAGE_PWT);

	    addr2 += PAGE_SIZE;
	}
	__flush_tlb_all();
    }

Mehdi

_________________________________________________________________
Send and receive Hotmail on your mobile device: http://mobile.msn.com


^ permalink raw reply	[flat|nested] 2+ messages in thread

* Fwd: PTE question
@ 2002-09-20 17:42 Mehdi Hashemian
  0 siblings, 0 replies; 2+ messages in thread
From: Mehdi Hashemian @ 2002-09-20 17:42 UTC (permalink / raw)
  To: linux-kernel

Hello,

I posted this question a few days ago but I did not get any response back. 
If I sent my question on the wrong email list, I appreciate if someone gives 
me some hints on what email list I should send my email to.

Thanks
Mehdi

----Original Message Follows----
From: "Mehdi Hashemian" <mhashemian@hotmail.com>
To: linux-kernel@vger.kernel.org
Subject: PTE question
Date: Wed, 18 Sep 2002 18:52:25 -0700

Hello,

Appreciate if someone checks this piece of code. I try to diable cache and 
write-through bits in PTE but somehow PTE address is within first 16MB of 
memory (DMA_ZONE) and later when Kernel tries to allocate more pages, it 
chooses the same address range and this piece of code corrupts memory by 
ORing these bits. Any help appreciated!

    {
        addr = __get_dma_pages(priority, order);

        int npages = __get_npages(order);
	unsigned long addr2 = addr;
	pgd_t *pgd;
	pmd_t *pmd;
	pte_t *pte;
	int i;

	for (i = 0; i < npages; i++)
	{
	    pgd = pgd_offset(&init_mm, addr2);
	    pmd = pmd_offset(pgd, addr2);
	    pte = pte_offset(pmd, addr2);
	    pte_val(*pte) |= (_PAGE_PCD | _PAGE_PWT);

	    addr2 += PAGE_SIZE;
	}
	__flush_tlb_all();
    }

Mehdi

_________________________________________________________________
Join the world’s largest e-mail service with MSN Hotmail. 
http://www.hotmail.com


^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2002-09-20 20:04 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-09-20 20:09 Fwd: PTE question Mehdi Hashemian
  -- strict thread matches above, loose matches on Subject: below --
2002-09-20 17:42 Mehdi Hashemian

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®