* [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support
2023-10-04 15:11 [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
@ 2023-10-04 14:20 ` Chen Wang
2023-10-04 14:27 ` Chen Wang
2023-10-04 15:14 ` [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
1 sibling, 1 reply; 6+ messages in thread
From: Chen Wang @ 2023-10-04 14:20 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley
The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..d4df7b5d0f16 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,11 @@ config SOC_SIFIVE
help
This enables support for SiFive SoC platform hardware.
+config ARCH_SOPHGO
+ bool "Sophgo SoCs"
+ help
+ This enables support for Sophgo SoC platform hardware.
+
config ARCH_STARFIVE
def_bool SOC_STARFIVE
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support
2023-10-04 14:20 ` [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
@ 2023-10-04 14:27 ` Chen Wang
0 siblings, 0 replies; 6+ messages in thread
From: Chen Wang @ 2023-10-04 14:27 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Conor Dooley
Sorry, please ignore this email due to not sending out in thread.
On 2023/10/4 22:20, Chen Wang wrote:
> The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
> cores.
>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Acked-by: Chao Wei <chao.wei@sophgo.com>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> arch/riscv/Kconfig.socs | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 6833d01e2e70..d4df7b5d0f16 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -22,6 +22,11 @@ config SOC_SIFIVE
> help
> This enables support for SiFive SoC platform hardware.
>
> +config ARCH_SOPHGO
> + bool "Sophgo SoCs"
> + help
> + This enables support for Sophgo SoC platform hardware.
> +
> config ARCH_STARFIVE
> def_bool SOC_STARFIVE
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support
@ 2023-10-04 15:11 Chen Wang
2023-10-04 14:20 ` [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
2023-10-04 15:14 ` [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
0 siblings, 2 replies; 6+ messages in thread
From: Chen Wang @ 2023-10-04 15:11 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang
From: Chen Wang <unicorn_wang@outlook.com>
Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
in a standard mATX form factor. Add minimal device
tree files for the SG2042 SOC and the Milk-V Pioneer board.
Now only support basic uart drivers to boot up into a basic console.
Thanks,
Chen
---
Changes in v4:
The patch series is based on v6.6-rc1. You can simply review or test
the patches at the link [6].
- Update bindings files for sg2042 clint as per intput from reviewers:
- rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer
to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
- rename compatible strings accordingly.
- Update dts as per input from reviewers: don't use macro for cpus's isa
properties; use new compatible strings for mtimer/mswi of clint.
- Use only one email-address for SoB.
Changes in v3 [v3]:
The patch series is based on v6.6-rc1. You can simply review or test
the patches at the link [5].
- add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
- updated maintainers info. for sophgo devicetree
- remove the quirk changes for uart
- updated dts, such as:
- add "riscv,isa-base"/"riscv,isa-extensions" for cpus
- update l2 cache node's name
- remove memory and pmu nodes
- fixed other issues as per input from reviewers.
Changes in v2 [v2]:
The patch series is based on v6.6-rc1. You can simply review or test
the patches at the link [4].
- Improve format for comment of commitments as per input from last review.
- Improve format of DTS as per input from last review.
- Remove numa related stuff from DTS. This part is just for optimization, may
add it later if really needed.
Changes in v1:
The patch series is based on v6.6-rc1. Due to it is not sent in thread,
I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
quick reference. You can simply review or test the patches at the link [3].
[1]: https://milkv.io/pioneer
[2]: https://en.sophgo.com/product/introduce/sg2042.html
[3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
[4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
[5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
[6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
[v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
[v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
[v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
[v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
[v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
[v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
[v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
[v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
[v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
[v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
[v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
[v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
[v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
[v2]:https://lore.kernel.org/linux-riscv/cover.1695189879.git.wangchen20@iscas.ac.cn/
[v3]:https://lore.kernel.org/linux-riscv/cover.1695804418.git.unicornxw@gmail.com/
---
Chen Wang (8):
riscv: Add SOPHGO SOC family Kconfig support
dt-bindings: vendor-prefixes: add milkv/sophgo
dt-bindings: riscv: add sophgo sg2042 bindings
dt-bindings: riscv: Add T-HEAD C920 compatibles
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
riscv: dts: add initial Sophgo SG2042 SoC device tree
riscv: dts: sophgo: add Milk-V Pioneer board device tree
riscv: defconfig: enable SOPHGO SoC
Inochi Amaoto (2):
dt-bindings: timer: Add Sophgo sg2042 CLINT timer
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
.../sifive,plic-1.0.0.yaml | 1 +
.../thead,c900-aclint-mswi.yaml | 43 +
.../devicetree/bindings/riscv/cpus.yaml | 1 +
.../devicetree/bindings/riscv/sophgo.yaml | 28 +
.../timer/thead,c900-aclint-mtimer.yaml | 43 +
.../devicetree/bindings/vendor-prefixes.yaml | 4 +
MAINTAINERS | 7 +
arch/riscv/Kconfig.socs | 5 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 3 +
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++
.../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
arch/riscv/configs/defconfig | 1 +
14 files changed, 2481 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support
2023-10-04 15:11 [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-10-04 14:20 ` [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support Chen Wang
@ 2023-10-04 15:14 ` Chen Wang
2023-10-04 15:24 ` Conor Dooley
1 sibling, 1 reply; 6+ messages in thread
From: Chen Wang @ 2023-10-04 15:14 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang
Sorry, please ignore this email, it was sent out by mistake.
Chen Wang <unicornxw@gmail.com> 于2023年10月4日周三 23:11写道：
>
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Milk-V Pioneer [1] is a developer motherboard based on SOPHON SG2042 [2]
> in a standard mATX form factor. Add minimal device
> tree files for the SG2042 SOC and the Milk-V Pioneer board.
>
> Now only support basic uart drivers to boot up into a basic console.
>
> Thanks,
> Chen
>
> ---
>
> Changes in v4:
> The patch series is based on v6.6-rc1. You can simply review or test
> the patches at the link [6].
> - Update bindings files for sg2042 clint as per intput from reviewers:
> - rename filename from sophgo,sg2042-clint-mswi/sg2042-clint-mtimer
> to thead,c900-aclint-mswi/thead,c900-aclint-mtimer.
> - rename compatible strings accordingly.
> - Update dts as per input from reviewers: don't use macro for cpus's isa
> properties; use new compatible strings for mtimer/mswi of clint.
> - Use only one email-address for SoB.
>
> Changes in v3 [v3]:
> The patch series is based on v6.6-rc1. You can simply review or test
> the patches at the link [5].
> - add new vendor specific compatible strings to identify timer/mswi for sg2042 clint
> - updated maintainers info. for sophgo devicetree
> - remove the quirk changes for uart
> - updated dts, such as:
> - add "riscv,isa-base"/"riscv,isa-extensions" for cpus
> - update l2 cache node's name
> - remove memory and pmu nodes
> - fixed other issues as per input from reviewers.
>
> Changes in v2 [v2]:
> The patch series is based on v6.6-rc1. You can simply review or test
> the patches at the link [4].
> - Improve format for comment of commitments as per input from last review.
> - Improve format of DTS as per input from last review.
> - Remove numa related stuff from DTS. This part is just for optimization, may
> add it later if really needed.
>
> Changes in v1:
> The patch series is based on v6.6-rc1. Due to it is not sent in thread,
> I have listed permlinks of the patchset [v1-0/12] ~ [v1-12/12] here for
> quick reference. You can simply review or test the patches at the link [3].
>
> [1]: https://milkv.io/pioneer
> [2]: https://en.sophgo.com/product/introduce/sg2042.html
> [3]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal
> [4]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v2
> [5]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v3
> [6]: https://github.com/unicornx/linux-riscv/commits/milkv-pioneer-minimal-v4
> [v1-0/12]:https://lore.kernel.org/linux-riscv/20230915070856.117514-1-wangchen20@iscas.ac.cn/
> [v1-1/12]:https://lore.kernel.org/linux-riscv/20230915071005.117575-1-wangchen20@iscas.ac.cn/
> [v1-2/12]:https://lore.kernel.org/linux-riscv/20230915071409.117692-1-wangchen20@iscas.ac.cn/
> [v1-3/12]:https://lore.kernel.org/linux-riscv/20230915072242.117935-1-wangchen20@iscas.ac.cn/
> [v1-4/12]:https://lore.kernel.org/linux-riscv/20230915072333.117991-1-wangchen20@iscas.ac.cn/
> [v1-5/12]:https://lore.kernel.org/linux-riscv/20230915072358.118045-1-wangchen20@iscas.ac.cn/
> [v1-6/12]:https://lore.kernel.org/linux-riscv/20230915072415.118100-1-wangchen20@iscas.ac.cn/
> [v1-7/12]:https://lore.kernel.org/linux-riscv/20230915072431.118154-1-wangchen20@iscas.ac.cn/
> [v1-8/12]:https://lore.kernel.org/linux-riscv/20230915072451.118209-1-wangchen20@iscas.ac.cn/
> [v1-9/12]:https://lore.kernel.org/linux-riscv/20230915072517.118266-1-wangchen20@iscas.ac.cn/
> [v1-10/12]:https://lore.kernel.org/linux-riscv/20230915072558.118325-1-wangchen20@iscas.ac.cn/
> [v1-11/12]:https://lore.kernel.org/linux-riscv/20230915072624.118388-1-wangchen20@iscas.ac.cn/
> [v1-12/12]:https://lore.kernel.org/linux-riscv/20230915072653.118448-1-wangchen20@iscas.ac.cn/
> [v2]:https://lore.kernel.org/linux-riscv/cover.1695189879.git.wangchen20@iscas.ac.cn/
> [v3]:https://lore.kernel.org/linux-riscv/cover.1695804418.git.unicornxw@gmail.com/
>
> ---
>
> Chen Wang (8):
> riscv: Add SOPHGO SOC family Kconfig support
> dt-bindings: vendor-prefixes: add milkv/sophgo
> dt-bindings: riscv: add sophgo sg2042 bindings
> dt-bindings: riscv: Add T-HEAD C920 compatibles
> dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC
> riscv: dts: add initial Sophgo SG2042 SoC device tree
> riscv: dts: sophgo: add Milk-V Pioneer board device tree
> riscv: defconfig: enable SOPHGO SoC
>
> Inochi Amaoto (2):
> dt-bindings: timer: Add Sophgo sg2042 CLINT timer
> dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi
>
> .../sifive,plic-1.0.0.yaml | 1 +
> .../thead,c900-aclint-mswi.yaml | 43 +
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../devicetree/bindings/riscv/sophgo.yaml | 28 +
> .../timer/thead,c900-aclint-mtimer.yaml | 43 +
> .../devicetree/bindings/vendor-prefixes.yaml | 4 +
> MAINTAINERS | 7 +
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/sophgo/Makefile | 3 +
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++
> .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 +
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 325 +++
> arch/riscv/configs/defconfig | 1 +
> 14 files changed, 2481 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml
> create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml
> create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> create mode 100644 arch/riscv/boot/dts/sophgo/Makefile
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi
>
>
> base-commit: 0bb80ecc33a8fb5a682236443c1e740d5c917d1d
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support
2023-10-04 15:14 ` [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
@ 2023-10-04 15:24 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2023-10-04 15:24 UTC (permalink / raw)
To: Chen Wang
Cc: aou, chao.wei, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel, Chen Wang
[-- Attachment #1: Type: text/plain, Size: 252 bytes --]
On Wed, Oct 04, 2023 at 11:14:54PM +0800, Chen Wang wrote:
> Sorry, please ignore this email, it was sent out by mistake.
What are you doing that this has happened twice today?
Don't you just do `git send-email /path/to/directory/containing/patches`?
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 01/10] riscv: Add SOPHGO SOC family Kconfig support
2023-10-04 15:37 Chen Wang
@ 2023-10-04 15:38 ` Chen Wang
0 siblings, 0 replies; 6+ messages in thread
From: Chen Wang @ 2023-10-04 15:38 UTC (permalink / raw)
To: aou, chao.wei, conor, devicetree, guoren, jszhang,
krzysztof.kozlowski+dt, linux-kernel, linux-riscv, palmer,
paul.walmsley, robh+dt, xiaoguang.xing, apatel
Cc: Chen Wang, Conor Dooley
From: Chen Wang <unicorn_wang@outlook.com>
The first SoC in the SOPHGO series is SG2042, which contains 64 RISC-V
cores.
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Chao Wei <chao.wei@sophgo.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 6833d01e2e70..d4df7b5d0f16 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -22,6 +22,11 @@ config SOC_SIFIVE
help
This enables support for SiFive SoC platform hardware.
+config ARCH_SOPHGO
+ bool "Sophgo SoCs"
+ help
+ This enables support for Sophgo SoC platform hardware.
+
config ARCH_STARFIVE
def_bool SOC_STARFIVE
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-10-04 15:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-04 15:11 [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
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2023-10-04 14:27 ` Chen Wang
2023-10-04 15:14 ` [PATCH v4 00/10] Add Milk-V Pioneer RISC-V board support Chen Wang
2023-10-04 15:24 ` Conor Dooley
2023-10-04 15:37 Chen Wang
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