* [PATCH v2 0/2] reset: canaan: add Kendryte K230 reset support
@ 2025-04-19 17:09 Junhui Liu
2025-04-19 17:09 ` [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst Junhui Liu
2025-04-19 17:09 ` [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230 Junhui Liu
0 siblings, 2 replies; 10+ messages in thread
From: Junhui Liu @ 2025-04-19 17:09 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Junhui Liu
Cc: devicetree, linux-kernel, linux-riscv, Conor Dooley
This patch series add reset controller support for the Canaan Kendryte
K230 SoC.
Tested on CanMV-K230-V1.1 board. Some of the HW_DONE and SW_DONE reset
type was tested by reseting the submodule and checking the reset
register value[1]. The CPU reset type was tested by a temporary rproc
driver[2][3].
link: https://gist.github.com/pigmoral/cc45de673775575750ac7fe49d4456a2 [1]
link: https://github.com/pigmoral/linux/tree/k230/rproc-cpu0 [2]
link: https://github.com/pigmoral/linux/tree/k230/rproc-cpu1 [3]
---
Changes in v2:
- Turn to_k230_rst from macro to inline function
- Use guard to replace spin_lock_irqsave and spin_unlock_irqrestore
- Remove assert and deassert operations for self-clearing reset types,
only reserve the reset operation
- Add delay to accommodate the reset time
- Remove blank line inside read-modify-write operations
- Remove redundant default case in enum switch
- Update copyright dates and my email address
- Link to v1: https://lore.kernel.org/r/20240924-k230-reset-v1-0-d0cdc11989eb@outlook.com
---
Junhui Liu (2):
dt-bindings: reset: add support for canaan,k230-rst
reset: canaan: add reset driver for Kendryte K230
.../devicetree/bindings/reset/canaan,k230-rst.yaml | 39 +++
drivers/reset/Kconfig | 9 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-k230.c | 355 +++++++++++++++++++++
include/dt-bindings/reset/canaan,k230-rst.h | 90 ++++++
5 files changed, 494 insertions(+)
---
base-commit: 8560697b23dc2f405cb463af2b17256a9888129d
change-id: 20250404-k230-reset-32987c6f0ed5
Best regards,
--
Junhui Liu <junhui.liu@pigmoral.tech>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst
2025-04-19 17:09 [PATCH v2 0/2] reset: canaan: add Kendryte K230 reset support Junhui Liu
@ 2025-04-19 17:09 ` Junhui Liu
2025-04-23 2:21 ` Chen Wang
2025-04-19 17:09 ` [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230 Junhui Liu
1 sibling, 1 reply; 10+ messages in thread
From: Junhui Liu @ 2025-04-19 17:09 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Junhui Liu
Cc: devicetree, linux-kernel, linux-riscv, Conor Dooley
Introduces a reset controller driver for the Kendryte K230 SoC,
resposible for managing the reset functionality of the CPUs and
various sub-modules.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
.../devicetree/bindings/reset/canaan,k230-rst.yaml | 39 ++++++++++
include/dt-bindings/reset/canaan,k230-rst.h | 90 ++++++++++++++++++++++
2 files changed, 129 insertions(+)
diff --git a/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..d352d0e12d8106a232bb5e6d7e138697d2106937
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/canaan,k230-rst.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Canaan Kendryte K230 Reset Controller
+
+maintainers:
+ - Junhui Liu <junhui.liu@pigmoral.tech>
+
+description:
+ The Canaan Kendryte K230 reset controller is part of the SoC's system
+ controller and controls the reset registers for CPUs and various peripherals.
+
+properties:
+ compatible:
+ const: canaan,k230-rst
+
+ reg:
+ maxItems: 1
+
+ '#reset-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ reset-controller@91101000 {
+ compatible = "canaan,k230-rst";
+ reg = <0x91101000 0x1000>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindings/reset/canaan,k230-rst.h
new file mode 100644
index 0000000000000000000000000000000000000000..53e3fd8177071aef8983c631706d67ac86ab645b
--- /dev/null
+++ b/include/dt-bindings/reset/canaan,k230-rst.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd
+ * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_
+#define _DT_BINDINGS_CANAAN_K230_RST_H_
+
+#define RST_CPU0 0
+#define RST_CPU1 1
+#define RST_CPU0_FLUSH 2
+#define RST_CPU1_FLUSH 3
+#define RST_AI 4
+#define RST_VPU 5
+#define RST_HS 6
+#define RST_HS_AHB 7
+#define RST_SDIO0 8
+#define RST_SDIO1 9
+#define RST_SDIO_AXI 10
+#define RST_USB0 11
+#define RST_USB1 12
+#define RST_USB0_AHB 13
+#define RST_USB1_AHB 14
+#define RST_SPI0 15
+#define RST_SPI1 16
+#define RST_SPI2 17
+#define RST_SEC 18
+#define RST_PDMA 19
+#define RST_SDMA 20
+#define RST_DECOMPRESS 21
+#define RST_SRAM 22
+#define RST_SHRM_AXIM 23
+#define RST_SHRM_AXIS 24
+#define RST_NONAI2D 25
+#define RST_MCTL 26
+#define RST_ISP 27
+#define RST_ISP_DW 28
+#define RST_DPU 29
+#define RST_DISP 30
+#define RST_GPU 31
+#define RST_AUDIO 32
+#define RST_TIMER0 33
+#define RST_TIMER1 34
+#define RST_TIMER2 35
+#define RST_TIMER3 36
+#define RST_TIMER4 37
+#define RST_TIMER5 38
+#define RST_TIMER_APB 39
+#define RST_HDI 40
+#define RST_WDT0 41
+#define RST_WDT1 42
+#define RST_WDT0_APB 43
+#define RST_WDT1_APB 44
+#define RST_TS_APB 45
+#define RST_MAILBOX 46
+#define RST_STC 47
+#define RST_PMU 48
+#define RST_LS_APB 49
+#define RST_UART0 50
+#define RST_UART1 51
+#define RST_UART2 52
+#define RST_UART3 53
+#define RST_UART4 54
+#define RST_I2C0 55
+#define RST_I2C1 56
+#define RST_I2C2 57
+#define RST_I2C3 58
+#define RST_I2C4 59
+#define RST_JAMLINK0_APB 60
+#define RST_JAMLINK1_APB 61
+#define RST_JAMLINK2_APB 62
+#define RST_JAMLINK3_APB 63
+#define RST_CODEC_APB 64
+#define RST_GPIO_DB 65
+#define RST_GPIO_APB 66
+#define RST_ADC 67
+#define RST_ADC_APB 68
+#define RST_PWM_APB 69
+#define RST_SHRM_APB 70
+#define RST_CSI0 71
+#define RST_CSI1 72
+#define RST_CSI2 73
+#define RST_CSI_DPHY 74
+#define RST_ISP_AHB 75
+#define RST_M0 76
+#define RST_M1 77
+#define RST_M2 78
+#define RST_SPI2AXI 79
+
+#endif
--
2.49.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230
2025-04-19 17:09 [PATCH v2 0/2] reset: canaan: add Kendryte K230 reset support Junhui Liu
2025-04-19 17:09 ` [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst Junhui Liu
@ 2025-04-19 17:09 ` Junhui Liu
2025-04-23 3:21 ` Chen Wang
2025-04-23 9:43 ` Philipp Zabel
1 sibling, 2 replies; 10+ messages in thread
From: Junhui Liu @ 2025-04-19 17:09 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Junhui Liu
Cc: devicetree, linux-kernel, linux-riscv
Add support for the resets on Canaan Kendryte K230 SoC. The driver
support CPU0, CPU1, L2 cache flush, hardware auto clear and software
clear resets.
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
The reset management module in the K230 SoC also provides reset time
control registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE,
the time period when reset is applyed/removed but the clock is stopped
can be set up to 15*0.25 = 3.75 us. For some RST_TYPE_HW_DONE cases, the
time period can be set up to 255*0.25 = 63.75 us. For RST_TYPE_FLUSH,
the reset bit will automatically cleared by hardware when flush done.
Although the current reset driver does not support configuration of
reset time registers, delay has been added to the assert, deassert and
reset functions to accommodate the longest reset time.
Besides, although some reset types have done bits, the reference manual
does not explicitly indicate whether the hardware removes reset or the
clock stop time period has passed when done bits toggle. Therefore, I
think it is a safer way to keep delay for reset types with done bits.
link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
---
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-k230.c | 355 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 365 insertions(+)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 99f6f9784e6865faddf8621ccfca095778c4dc47..248138ffba3bfbf859c74ba1aed7ba2f72819f7a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -140,6 +140,15 @@ config RESET_K210
Say Y if you want to control reset signals provided by this
controller.
+config RESET_K230
+ tristate "Reset controller driver for Canaan Kendryte K230 SoC"
+ depends on ARCH_CANAAN || COMPILE_TEST
+ depends on OF
+ help
+ Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
+ Say Y if you want to control reset signals provided by this
+ controller.
+
config RESET_LANTIQ
bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
default SOC_TYPE_XWAY
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 31f9904d13f9c3a107fc1ee1ec9f9baba016d101..13fe94531bea1eb91268b1804e1321b167815a4b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_K210) += reset-k210.o
+obj-$(CONFIG_RESET_K230) += reset-k230.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c
new file mode 100644
index 0000000000000000000000000000000000000000..492d2274893675b0ff1967426c8fa9e75aed1791
--- /dev/null
+++ b/drivers/reset/reset-k230.c
@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2016-2017 Linaro Ltd.
+ * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
+ * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <linux/cleanup.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+
+#include <dt-bindings/reset/canaan,k230-rst.h>
+
+/**
+ * enum k230_rst_type - K230 reset types
+ * @RST_TYPE_CPU0: Reset type for CPU0
+ * Automatically clears, has write enable and done bit, active high
+ * @RST_TYPE_CPU1: Reset type for CPU1
+ * Manually clears, has write enable and done bit, active high
+ * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
+ * Automatically clears, has write enable, no done bit, active high
+ * @RST_TYPE_HW_DONE: Reset type for hardware auto clear
+ * Automatically clears, no write enable, has done bit, active high
+ * @RST_TYPE_SW_DONE: Reset type for software manual clear
+ * Manually clears, no write enable and done bit,
+ * active high if ID is RST_SPI2AXI, otherwise active low
+ */
+enum k230_rst_type {
+ RST_TYPE_CPU0,
+ RST_TYPE_CPU1,
+ RST_TYPE_FLUSH,
+ RST_TYPE_HW_DONE,
+ RST_TYPE_SW_DONE,
+};
+
+struct k230_rst_map {
+ u32 offset;
+ enum k230_rst_type type;
+ u32 done;
+ u32 reset;
+};
+
+struct k230_rst {
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ void __iomem *base;
+ spinlock_t lock;
+};
+
+static const struct k230_rst_map k230_resets[] = {
+ [RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) },
+ [RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) },
+ [RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) },
+ [RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) },
+ [RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_HS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) },
+ [RST_HS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) },
+ [RST_SDIO0] = { 0x34, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
+ [RST_SDIO1] = { 0x34, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
+ [RST_SDIO_AXI] = { 0x34, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
+ [RST_USB0] = { 0x3c, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
+ [RST_USB1] = { 0x3c, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
+ [RST_USB0_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(30), BIT(0) },
+ [RST_USB1_AHB] = { 0x3c, RST_TYPE_HW_DONE, BIT(31), BIT(1) },
+ [RST_SPI0] = { 0x44, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
+ [RST_SPI1] = { 0x44, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
+ [RST_SPI2] = { 0x44, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
+ [RST_SEC] = { 0x4c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_PDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
+ [RST_SDMA] = { 0x54, RST_TYPE_HW_DONE, BIT(29), BIT(1) },
+ [RST_DECOMPRESS] = { 0x5c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_SRAM] = { 0x64, RST_TYPE_HW_DONE, BIT(28), BIT(0) },
+ [RST_SHRM_AXIM] = { 0x64, RST_TYPE_HW_DONE, BIT(30), BIT(2) },
+ [RST_SHRM_AXIS] = { 0x64, RST_TYPE_HW_DONE, BIT(31), BIT(3) },
+ [RST_NONAI2D] = { 0x6c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_MCTL] = { 0x74, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_ISP] = { 0x80, RST_TYPE_HW_DONE, BIT(29), BIT(6) },
+ [RST_ISP_DW] = { 0x80, RST_TYPE_HW_DONE, BIT(28), BIT(5) },
+ [RST_DPU] = { 0x88, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_DISP] = { 0x90, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_GPU] = { 0x98, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_AUDIO] = { 0xa4, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
+ [RST_TIMER0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(0) },
+ [RST_TIMER1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(1) },
+ [RST_TIMER2] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(2) },
+ [RST_TIMER3] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(3) },
+ [RST_TIMER4] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(4) },
+ [RST_TIMER5] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(5) },
+ [RST_TIMER_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(6) },
+ [RST_HDI] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(7) },
+ [RST_WDT0] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(12) },
+ [RST_WDT1] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(13) },
+ [RST_WDT0_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(14) },
+ [RST_WDT1_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(15) },
+ [RST_TS_APB] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(16) },
+ [RST_MAILBOX] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(17) },
+ [RST_STC] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(18) },
+ [RST_PMU] = { 0x20, RST_TYPE_SW_DONE, 0, BIT(19) },
+ [RST_LS_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(0) },
+ [RST_UART0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(1) },
+ [RST_UART1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(2) },
+ [RST_UART2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(3) },
+ [RST_UART3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(4) },
+ [RST_UART4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(5) },
+ [RST_I2C0] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(6) },
+ [RST_I2C1] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(7) },
+ [RST_I2C2] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(8) },
+ [RST_I2C3] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(9) },
+ [RST_I2C4] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(10) },
+ [RST_JAMLINK0_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(11) },
+ [RST_JAMLINK1_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(12) },
+ [RST_JAMLINK2_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(13) },
+ [RST_JAMLINK3_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(14) },
+ [RST_CODEC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(17) },
+ [RST_GPIO_DB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(18) },
+ [RST_GPIO_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(19) },
+ [RST_ADC] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(20) },
+ [RST_ADC_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(21) },
+ [RST_PWM_APB] = { 0x24, RST_TYPE_SW_DONE, 0, BIT(22) },
+ [RST_SHRM_APB] = { 0x64, RST_TYPE_SW_DONE, 0, BIT(1) },
+ [RST_CSI0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(0) },
+ [RST_CSI1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(1) },
+ [RST_CSI2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(2) },
+ [RST_CSI_DPHY] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(3) },
+ [RST_ISP_AHB] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(4) },
+ [RST_M0] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(7) },
+ [RST_M1] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(8) },
+ [RST_M2] = { 0x80, RST_TYPE_SW_DONE, 0, BIT(9) },
+ [RST_SPI2AXI] = { 0xa8, RST_TYPE_SW_DONE, 0, BIT(0) }
+};
+
+static inline struct k230_rst *to_k230_rst(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct k230_rst, rcdev);
+}
+
+static void k230_rst_clear_done(struct k230_rst *rstc, unsigned long id,
+ bool write_en)
+{
+ const struct k230_rst_map *rmap = &k230_resets[id];
+ u32 reg;
+
+ guard(spinlock_irqsave)(&rstc->lock);
+
+ reg = readl(rstc->base + rmap->offset);
+ reg |= rmap->done; /* write 1 to clear */
+ if (write_en)
+ reg |= rmap->done << 16;
+ writel(reg, rstc->base + rmap->offset);
+}
+
+static int k230_rst_wait_and_clear_done(struct k230_rst *rstc, unsigned long id,
+ bool write_en)
+{
+ const struct k230_rst_map *rmap = &k230_resets[id];
+ u32 reg;
+ int ret;
+
+ ret = readl_poll_timeout(rstc->base + rmap->offset, reg,
+ reg & rmap->done, 10, 1000);
+ if (ret) {
+ dev_err(rstc->dev, "Wait for reset done timeout\n");
+ return ret;
+ }
+
+ k230_rst_clear_done(rstc, id, write_en);
+
+ return 0;
+}
+
+static void k230_rst_update(struct k230_rst *rstc, unsigned long id,
+ bool assert, bool write_en, bool active_low)
+{
+ const struct k230_rst_map *rmap = &k230_resets[id];
+ u32 reg;
+
+ guard(spinlock_irqsave)(&rstc->lock);
+
+ reg = readl(rstc->base + rmap->offset);
+ if (assert ^ active_low)
+ reg |= rmap->reset;
+ else
+ reg &= ~rmap->reset;
+ if (write_en)
+ reg |= rmap->reset << 16;
+ writel(reg, rstc->base + rmap->offset);
+}
+
+static int k230_rst_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct k230_rst *rstc = to_k230_rst(rcdev);
+
+ switch (k230_resets[id].type) {
+ case RST_TYPE_CPU1:
+ k230_rst_update(rstc, id, true, true, false);
+ break;
+ case RST_TYPE_SW_DONE:
+ k230_rst_update(rstc, id, true, false,
+ id == RST_SPI2AXI ? false : true);
+ break;
+ case RST_TYPE_CPU0:
+ case RST_TYPE_FLUSH:
+ case RST_TYPE_HW_DONE:
+ return -EOPNOTSUPP;
+ }
+
+ /*
+ * The time period when reset is applied but the clock is stopped for
+ * RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay
+ * 10us to ensure proper reset timing.
+ */
+ udelay(10);
+
+ return 0;
+}
+
+static int k230_rst_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct k230_rst *rstc = to_k230_rst(rcdev);
+ int ret = 0;
+
+ switch (k230_resets[id].type) {
+ case RST_TYPE_CPU1:
+ k230_rst_update(rstc, id, false, true, false);
+ ret = k230_rst_wait_and_clear_done(rstc, id, true);
+ break;
+ case RST_TYPE_SW_DONE:
+ k230_rst_update(rstc, id, false, false,
+ id == RST_SPI2AXI ? false : true);
+ break;
+ case RST_TYPE_CPU0:
+ case RST_TYPE_FLUSH:
+ case RST_TYPE_HW_DONE:
+ return -EOPNOTSUPP;
+ }
+
+ /*
+ * The time period when reset is removed but the clock is stopped for
+ * RST_TYPE_CPU1 and RST_TYPE_SW_DONE can be set up to 3.75us. Delay
+ * 10us to ensure proper reset timing.
+ */
+ udelay(10);
+
+ return ret;
+}
+
+static int k230_rst_reset(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct k230_rst *rstc = to_k230_rst(rcdev);
+ const struct k230_rst_map *rmap = &k230_resets[id];
+ u32 reg;
+ int ret = 0;
+
+ switch (rmap->type) {
+ case RST_TYPE_CPU0:
+ k230_rst_clear_done(rstc, id, true);
+ k230_rst_update(rstc, id, true, true, false);
+ ret = k230_rst_wait_and_clear_done(rstc, id, true);
+
+ /*
+ * The time period when reset is applied and removed but the
+ * clock is stopped for RST_TYPE_CPU0 can be set up to 7.5us.
+ * Delay 10us to ensure proper reset timing.
+ */
+ udelay(10);
+
+ break;
+ case RST_TYPE_FLUSH:
+ k230_rst_update(rstc, id, true, true, false);
+
+ /* Wait flush request bit auto cleared by hardware */
+ ret = readl_poll_timeout(rstc->base + rmap->offset, reg,
+ !(reg & rmap->reset), 10, 1000);
+ if (ret)
+ dev_err(rstc->dev, "Wait for flush done timeout\n");
+
+ break;
+ case RST_TYPE_HW_DONE:
+ k230_rst_clear_done(rstc, id, false);
+ k230_rst_update(rstc, id, true, false, false);
+ ret = k230_rst_wait_and_clear_done(rstc, id, false);
+
+ /*
+ * The time period when reset is applied and removed but the
+ * clock is stopped for RST_TYPE_HW_DONE can be set up to
+ * 127.5us. Delay 200us to ensure proper reset timing.
+ */
+ udelay(200);
+
+ break;
+ case RST_TYPE_CPU1:
+ case RST_TYPE_SW_DONE:
+ k230_rst_assert(rcdev, id);
+ ret = k230_rst_deassert(rcdev, id);
+ break;
+ }
+
+ return ret;
+}
+
+static const struct reset_control_ops k230_rst_ops = {
+ .reset = k230_rst_reset,
+ .assert = k230_rst_assert,
+ .deassert = k230_rst_deassert,
+};
+
+static int k230_rst_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct k230_rst *rstc;
+
+ rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);
+ if (!rstc)
+ return -ENOMEM;
+
+ rstc->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rstc->base))
+ return PTR_ERR(rstc->base);
+
+ spin_lock_init(&rstc->lock);
+
+ rstc->dev = dev;
+ rstc->rcdev.owner = THIS_MODULE;
+ rstc->rcdev.ops = &k230_rst_ops;
+ rstc->rcdev.nr_resets = ARRAY_SIZE(k230_resets);
+ rstc->rcdev.of_node = dev->of_node;
+
+ return devm_reset_controller_register(dev, &rstc->rcdev);
+}
+
+static const struct of_device_id k230_rst_match[] = {
+ { .compatible = "canaan,k230-rst", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, k230_rst_match);
+
+static struct platform_driver k230_rst_driver = {
+ .probe = k230_rst_probe,
+ .driver = {
+ .name = "k230-rst",
+ .of_match_table = k230_rst_match,
+ }
+};
+module_platform_driver(k230_rst_driver);
+
+MODULE_AUTHOR("Junhui Liu <junhui.liu@pigmoral.tech>");
+MODULE_DESCRIPTION("Canaan K230 reset driver");
+MODULE_LICENSE("GPL");
--
2.49.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst
2025-04-19 17:09 ` [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst Junhui Liu
@ 2025-04-23 2:21 ` Chen Wang
2025-04-23 5:26 ` Junhui Liu
0 siblings, 1 reply; 10+ messages in thread
From: Chen Wang @ 2025-04-23 2:21 UTC (permalink / raw)
To: Junhui Liu, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv, Conor Dooley
hi，Junhui，
On 2025/4/20 1:09, Junhui Liu wrote:
> Introduces a reset controller driver for the Kendryte K230 SoC,
> resposible for managing the reset functionality of the CPUs and
> various sub-modules.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../devicetree/bindings/reset/canaan,k230-rst.yaml | 39 ++++++++++
> include/dt-bindings/reset/canaan,k230-rst.h | 90 ++++++++++++++++++++++
> 2 files changed, 129 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..d352d0e12d8106a232bb5e6d7e138697d2106937
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
> @@ -0,0 +1,39 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
The copyright statement in yaml and header files should be consistent.
Othres LGTM.
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Thanks,
Chen
[......]
> diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindings/reset/canaan,k230-rst.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..53e3fd8177071aef8983c631706d67ac86ab645b
> --- /dev/null
> +++ b/include/dt-bindings/reset/canaan,k230-rst.h
> @@ -0,0 +1,90 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
Here.
[....]
> +/*
> + * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd
> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_
> +#define _DT_BINDINGS_CANAAN_K230_RST_H_
> +
> +#define RST_CPU0 0
> +#define RST_CPU1 1
> +#define RST_CPU0_FLUSH 2
> +#define RST_CPU1_FLUSH 3
> +#define RST_AI 4
> +#define RST_VPU 5
> +#define RST_HS 6
> +#define RST_HS_AHB 7
> +#define RST_SDIO0 8
> +#define RST_SDIO1 9
> +#define RST_SDIO_AXI 10
> +#define RST_USB0 11
> +#define RST_USB1 12
> +#define RST_USB0_AHB 13
> +#define RST_USB1_AHB 14
> +#define RST_SPI0 15
> +#define RST_SPI1 16
> +#define RST_SPI2 17
> +#define RST_SEC 18
> +#define RST_PDMA 19
> +#define RST_SDMA 20
> +#define RST_DECOMPRESS 21
> +#define RST_SRAM 22
> +#define RST_SHRM_AXIM 23
> +#define RST_SHRM_AXIS 24
> +#define RST_NONAI2D 25
> +#define RST_MCTL 26
> +#define RST_ISP 27
> +#define RST_ISP_DW 28
> +#define RST_DPU 29
> +#define RST_DISP 30
> +#define RST_GPU 31
> +#define RST_AUDIO 32
> +#define RST_TIMER0 33
> +#define RST_TIMER1 34
> +#define RST_TIMER2 35
> +#define RST_TIMER3 36
> +#define RST_TIMER4 37
> +#define RST_TIMER5 38
> +#define RST_TIMER_APB 39
> +#define RST_HDI 40
> +#define RST_WDT0 41
> +#define RST_WDT1 42
> +#define RST_WDT0_APB 43
> +#define RST_WDT1_APB 44
> +#define RST_TS_APB 45
> +#define RST_MAILBOX 46
> +#define RST_STC 47
> +#define RST_PMU 48
> +#define RST_LS_APB 49
> +#define RST_UART0 50
> +#define RST_UART1 51
> +#define RST_UART2 52
> +#define RST_UART3 53
> +#define RST_UART4 54
> +#define RST_I2C0 55
> +#define RST_I2C1 56
> +#define RST_I2C2 57
> +#define RST_I2C3 58
> +#define RST_I2C4 59
> +#define RST_JAMLINK0_APB 60
> +#define RST_JAMLINK1_APB 61
> +#define RST_JAMLINK2_APB 62
> +#define RST_JAMLINK3_APB 63
> +#define RST_CODEC_APB 64
> +#define RST_GPIO_DB 65
> +#define RST_GPIO_APB 66
> +#define RST_ADC 67
> +#define RST_ADC_APB 68
> +#define RST_PWM_APB 69
> +#define RST_SHRM_APB 70
> +#define RST_CSI0 71
> +#define RST_CSI1 72
> +#define RST_CSI2 73
> +#define RST_CSI_DPHY 74
> +#define RST_ISP_AHB 75
> +#define RST_M0 76
> +#define RST_M1 77
> +#define RST_M2 78
> +#define RST_SPI2AXI 79
> +
> +#endif
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230
2025-04-19 17:09 ` [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230 Junhui Liu
@ 2025-04-23 3:21 ` Chen Wang
2025-04-23 5:36 ` Junhui Liu
2025-04-23 9:43 ` Philipp Zabel
1 sibling, 1 reply; 10+ messages in thread
From: Chen Wang @ 2025-04-23 3:21 UTC (permalink / raw)
To: Junhui Liu, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv
Hi, Junhui,
On 2025/4/20 1:09, Junhui Liu wrote:
> Add support for the resets on Canaan Kendryte K230 SoC. The driver
> support CPU0, CPU1, L2 cache flush, hardware auto clear and software
> clear resets.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>
> ---
> The reset management module in the K230 SoC also provides reset time
> control registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE,
> the time period when reset is applyed/removed but the clock is stopped
> can be set up to 15*0.25 = 3.75 us. For some RST_TYPE_HW_DONE cases, the
> time period can be set up to 255*0.25 = 63.75 us. For RST_TYPE_FLUSH,
> the reset bit will automatically cleared by hardware when flush done.
>
> Although the current reset driver does not support configuration of
> reset time registers, delay has been added to the assert, deassert and
> reset functions to accommodate the longest reset time.
>
> Besides, although some reset types have done bits, the reference manual
> does not explicitly indicate whether the hardware removes reset or the
> clock stop time period has passed when done bits toggle. Therefore, I
> think it is a safer way to keep delay for reset types with done bits.
>
> link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
Regards these notes, please move it to the beginning of source code, see
example: drivers/pwm/pwm-sophgo-sg2042.c
> ---
> drivers/reset/Kconfig | 9 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-k230.c | 355 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 365 insertions(+)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 99f6f9784e6865faddf8621ccfca095778c4dc47..248138ffba3bfbf859c74ba1aed7ba2f72819f7a 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -140,6 +140,15 @@ config RESET_K210
> Say Y if you want to control reset signals provided by this
> controller.
>
> +config RESET_K230
> + tristate "Reset controller driver for Canaan Kendryte K230 SoC"
> + depends on ARCH_CANAAN || COMPILE_TEST
> + depends on OF
> + help
> + Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
> + Say Y if you want to control reset signals provided by this
> + controller.
> +
> config RESET_LANTIQ
> bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
> default SOC_TYPE_XWAY
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 31f9904d13f9c3a107fc1ee1ec9f9baba016d101..13fe94531bea1eb91268b1804e1321b167815a4b 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
> obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
> obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
> obj-$(CONFIG_RESET_K210) += reset-k210.o
> +obj-$(CONFIG_RESET_K230) += reset-k230.o
> obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
> diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..492d2274893675b0ff1967426c8fa9e75aed1791
> --- /dev/null
> +++ b/drivers/reset/reset-k230.c
> @@ -0,0 +1,355 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2016-2017 Linaro Ltd.
Linaro? Are you sure?
> + * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#include <linux/cleanup.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/reset/canaan,k230-rst.h>
> +
> +/**
> + * enum k230_rst_type - K230 reset types
> + * @RST_TYPE_CPU0: Reset type for CPU0
> + * Automatically clears, has write enable and done bit, active high
> + * @RST_TYPE_CPU1: Reset type for CPU1
> + * Manually clears, has write enable and done bit, active high
> + * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
> + * Automatically clears, has write enable, no done bit, active high
> + * @RST_TYPE_HW_DONE: Reset type for hardware auto clear
> + * Automatically clears, no write enable, has done bit, active high
> + * @RST_TYPE_SW_DONE: Reset type for software manual clear
> + * Manually clears, no write enable and done bit,
> + * active high if ID is RST_SPI2AXI, otherwise active low
> + */
> +enum k230_rst_type {
> + RST_TYPE_CPU0,
> + RST_TYPE_CPU1,
> + RST_TYPE_FLUSH,
> + RST_TYPE_HW_DONE,
> + RST_TYPE_SW_DONE,
> +};
> +
> +struct k230_rst_map {
> + u32 offset;
> + enum k230_rst_type type;
> + u32 done;
> + u32 reset;
> +};
> +
> +struct k230_rst {
> + struct reset_controller_dev rcdev;
> + struct device *dev;
Why don't usercdev.dev to store the dev, so we can save a pointer.
> + void __iomem *base;
> + spinlock_t lock;
> +};
[......]
Thanks,
Chen
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst
2025-04-23 2:21 ` Chen Wang
@ 2025-04-23 5:26 ` Junhui Liu
0 siblings, 0 replies; 10+ messages in thread
From: Junhui Liu @ 2025-04-23 5:26 UTC (permalink / raw)
To: Chen Wang, Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv, Conor Dooley
Hi Chen,
Thanks for your review.
On 23/04/2025 10:21, Chen Wang wrote:
> hi，Junhui，
>
> On 2025/4/20 1:09, Junhui Liu wrote:
>> Introduces a reset controller driver for the Kendryte K230 SoC,
>> resposible for managing the reset functionality of the CPUs and
>> various sub-modules.
>>
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>> ---
>> .../devicetree/bindings/reset/canaan,k230-rst.yaml | 39 ++++++++++
>> include/dt-bindings/reset/canaan,k230-rst.h | 90 ++++++++++++++++++++++
>> 2 files changed, 129 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..d352d0e12d8106a232bb5e6d7e138697d2106937
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/reset/canaan,k230-rst.yaml
>> @@ -0,0 +1,39 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>
> The copyright statement in yaml and header files should be consistent.
>
> Othres LGTM.
>
> Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
>
> Thanks,
>
> Chen
>
> [......]
>> diff --git a/include/dt-bindings/reset/canaan,k230-rst.h b/include/dt-bindings/reset/canaan,k230-rst.h
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..53e3fd8177071aef8983c631706d67ac86ab645b
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/canaan,k230-rst.h
>> @@ -0,0 +1,90 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>
> Here.
>
I will update it to (GPL-2.0-only OR BSD-2-Clause) in next version.
> [....]
>
>
>> +/*
>> + * Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd
>> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
>> + */
>> +#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_
>> +#define _DT_BINDINGS_CANAAN_K230_RST_H_
>> +
>> +#define RST_CPU0 0
>> +#define RST_CPU1 1
>> +#define RST_CPU0_FLUSH 2
>> +#define RST_CPU1_FLUSH 3
>> +#define RST_AI 4
>> +#define RST_VPU 5
>> +#define RST_HS 6
>> +#define RST_HS_AHB 7
>> +#define RST_SDIO0 8
>> +#define RST_SDIO1 9
>> +#define RST_SDIO_AXI 10
>> +#define RST_USB0 11
>> +#define RST_USB1 12
>> +#define RST_USB0_AHB 13
>> +#define RST_USB1_AHB 14
>> +#define RST_SPI0 15
>> +#define RST_SPI1 16
>> +#define RST_SPI2 17
>> +#define RST_SEC 18
>> +#define RST_PDMA 19
>> +#define RST_SDMA 20
>> +#define RST_DECOMPRESS 21
>> +#define RST_SRAM 22
>> +#define RST_SHRM_AXIM 23
>> +#define RST_SHRM_AXIS 24
>> +#define RST_NONAI2D 25
>> +#define RST_MCTL 26
>> +#define RST_ISP 27
>> +#define RST_ISP_DW 28
>> +#define RST_DPU 29
>> +#define RST_DISP 30
>> +#define RST_GPU 31
>> +#define RST_AUDIO 32
>> +#define RST_TIMER0 33
>> +#define RST_TIMER1 34
>> +#define RST_TIMER2 35
>> +#define RST_TIMER3 36
>> +#define RST_TIMER4 37
>> +#define RST_TIMER5 38
>> +#define RST_TIMER_APB 39
>> +#define RST_HDI 40
>> +#define RST_WDT0 41
>> +#define RST_WDT1 42
>> +#define RST_WDT0_APB 43
>> +#define RST_WDT1_APB 44
>> +#define RST_TS_APB 45
>> +#define RST_MAILBOX 46
>> +#define RST_STC 47
>> +#define RST_PMU 48
>> +#define RST_LS_APB 49
>> +#define RST_UART0 50
>> +#define RST_UART1 51
>> +#define RST_UART2 52
>> +#define RST_UART3 53
>> +#define RST_UART4 54
>> +#define RST_I2C0 55
>> +#define RST_I2C1 56
>> +#define RST_I2C2 57
>> +#define RST_I2C3 58
>> +#define RST_I2C4 59
>> +#define RST_JAMLINK0_APB 60
>> +#define RST_JAMLINK1_APB 61
>> +#define RST_JAMLINK2_APB 62
>> +#define RST_JAMLINK3_APB 63
>> +#define RST_CODEC_APB 64
>> +#define RST_GPIO_DB 65
>> +#define RST_GPIO_APB 66
>> +#define RST_ADC 67
>> +#define RST_ADC_APB 68
>> +#define RST_PWM_APB 69
>> +#define RST_SHRM_APB 70
>> +#define RST_CSI0 71
>> +#define RST_CSI1 72
>> +#define RST_CSI2 73
>> +#define RST_CSI_DPHY 74
>> +#define RST_ISP_AHB 75
>> +#define RST_M0 76
>> +#define RST_M1 77
>> +#define RST_M2 78
>> +#define RST_SPI2AXI 79
>> +
>> +#endif
>>
--
Best regards,
Junhui Liu
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230
2025-04-23 3:21 ` Chen Wang
@ 2025-04-23 5:36 ` Junhui Liu
2025-04-23 5:55 ` Chen Wang
0 siblings, 1 reply; 10+ messages in thread
From: Junhui Liu @ 2025-04-23 5:36 UTC (permalink / raw)
To: Chen Wang, Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv
Hi Chen,
Thanks for your review.
On 23/04/2025 11:21, Chen Wang wrote:
> Hi, Junhui,
>
>
> On 2025/4/20 1:09, Junhui Liu wrote:
>> Add support for the resets on Canaan Kendryte K230 SoC. The driver
>> support CPU0, CPU1, L2 cache flush, hardware auto clear and software
>> clear resets.
>>
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>>
>> ---
>> The reset management module in the K230 SoC also provides reset time
>> control registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE,
>> the time period when reset is applyed/removed but the clock is stopped
>> can be set up to 15*0.25 = 3.75 us. For some RST_TYPE_HW_DONE cases, the
>> time period can be set up to 255*0.25 = 63.75 us. For RST_TYPE_FLUSH,
>> the reset bit will automatically cleared by hardware when flush done.
>>
>> Although the current reset driver does not support configuration of
>> reset time registers, delay has been added to the assert, deassert and
>> reset functions to accommodate the longest reset time.
>>
>> Besides, although some reset types have done bits, the reference manual
>> does not explicitly indicate whether the hardware removes reset or the
>> clock stop time period has passed when done bits toggle. Therefore, I
>> think it is a safer way to keep delay for reset types with done bits.
>>
>> link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
> Regards these notes, please move it to the beginning of source code, see
> example: drivers/pwm/pwm-sophgo-sg2042.c
>> ---
>> drivers/reset/Kconfig | 9 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-k230.c | 355 +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 365 insertions(+)
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 99f6f9784e6865faddf8621ccfca095778c4dc47..248138ffba3bfbf859c74ba1aed7ba2f72819f7a 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -140,6 +140,15 @@ config RESET_K210
>> Say Y if you want to control reset signals provided by this
>> controller.
>>
>> +config RESET_K230
>> + tristate "Reset controller driver for Canaan Kendryte K230 SoC"
>> + depends on ARCH_CANAAN || COMPILE_TEST
>> + depends on OF
>> + help
>> + Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
>> + Say Y if you want to control reset signals provided by this
>> + controller.
>> +
>> config RESET_LANTIQ
>> bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
>> default SOC_TYPE_XWAY
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 31f9904d13f9c3a107fc1ee1ec9f9baba016d101..13fe94531bea1eb91268b1804e1321b167815a4b 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
>> obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
>> obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
>> obj-$(CONFIG_RESET_K210) += reset-k210.o
>> +obj-$(CONFIG_RESET_K230) += reset-k230.o
>> obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
>> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>> obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
>> diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..492d2274893675b0ff1967426c8fa9e75aed1791
>> --- /dev/null
>> +++ b/drivers/reset/reset-k230.c
>> @@ -0,0 +1,355 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (C) 2016-2017 Linaro Ltd.
> Linaro? Are you sure?
Actually, I kept this from vendor's code.
link: https://github.com/kendryte/k230_sdk/blob/v1.9/src/little/linux/drivers/reset/canaan/reset-k230.c#L19
>> + * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
>> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
>> + */
>> +
>> +#include <linux/cleanup.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/spinlock.h>
>> +
>> +#include <dt-bindings/reset/canaan,k230-rst.h>
>> +
>> +/**
>> + * enum k230_rst_type - K230 reset types
>> + * @RST_TYPE_CPU0: Reset type for CPU0
>> + * Automatically clears, has write enable and done bit, active high
>> + * @RST_TYPE_CPU1: Reset type for CPU1
>> + * Manually clears, has write enable and done bit, active high
>> + * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
>> + * Automatically clears, has write enable, no done bit, active high
>> + * @RST_TYPE_HW_DONE: Reset type for hardware auto clear
>> + * Automatically clears, no write enable, has done bit, active high
>> + * @RST_TYPE_SW_DONE: Reset type for software manual clear
>> + * Manually clears, no write enable and done bit,
>> + * active high if ID is RST_SPI2AXI, otherwise active low
>> + */
>> +enum k230_rst_type {
>> + RST_TYPE_CPU0,
>> + RST_TYPE_CPU1,
>> + RST_TYPE_FLUSH,
>> + RST_TYPE_HW_DONE,
>> + RST_TYPE_SW_DONE,
>> +};
>> +
>> +struct k230_rst_map {
>> + u32 offset;
>> + enum k230_rst_type type;
>> + u32 done;
>> + u32 reset;
>> +};
>> +
>> +struct k230_rst {
>> + struct reset_controller_dev rcdev;
>> + struct device *dev;
>
> Why don't usercdev.dev to store the dev, so we can save a pointer.
Thanks for your reminder, I will store it in rcdev.dev.
>
>> + void __iomem *base;
>> + spinlock_t lock;
>> +};
>
> [......]
>
> Thanks,
>
> Chen
--
Best regards,
Junhui Liu
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230
2025-04-23 5:36 ` Junhui Liu
@ 2025-04-23 5:55 ` Chen Wang
0 siblings, 0 replies; 10+ messages in thread
From: Chen Wang @ 2025-04-23 5:55 UTC (permalink / raw)
To: Junhui Liu, Philipp Zabel, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv
On 2025/4/23 13:36, Junhui Liu wrote:
> Hi Chen,
>
> Thanks for your review.
>
> On 23/04/2025 11:21, Chen Wang wrote:
>> Hi, Junhui,
>>
>>
>> On 2025/4/20 1:09, Junhui Liu wrote:
>>> Add support for the resets on Canaan Kendryte K230 SoC. The driver
>>> support CPU0, CPU1, L2 cache flush, hardware auto clear and software
>>> clear resets.
>>>
>>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>>>
>>> ---
>>> The reset management module in the K230 SoC also provides reset time
>>> control registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE,
>>> the time period when reset is applyed/removed but the clock is stopped
>>> can be set up to 15*0.25 = 3.75 us. For some RST_TYPE_HW_DONE cases, the
>>> time period can be set up to 255*0.25 = 63.75 us. For RST_TYPE_FLUSH,
>>> the reset bit will automatically cleared by hardware when flush done.
>>>
>>> Although the current reset driver does not support configuration of
>>> reset time registers, delay has been added to the assert, deassert and
>>> reset functions to accommodate the longest reset time.
>>>
>>> Besides, although some reset types have done bits, the reference manual
>>> does not explicitly indicate whether the hardware removes reset or the
>>> clock stop time period has passed when done bits toggle. Therefore, I
>>> think it is a safer way to keep delay for reset types with done bits.
>>>
>>> link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
>> Regards these notes, please move it to the beginning of source code, see
>> example: drivers/pwm/pwm-sophgo-sg2042.c
>>> ---
>>> drivers/reset/Kconfig | 9 ++
>>> drivers/reset/Makefile | 1 +
>>> drivers/reset/reset-k230.c | 355 +++++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 365 insertions(+)
>>>
>>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>>> index 99f6f9784e6865faddf8621ccfca095778c4dc47..248138ffba3bfbf859c74ba1aed7ba2f72819f7a 100644
>>> --- a/drivers/reset/Kconfig
>>> +++ b/drivers/reset/Kconfig
>>> @@ -140,6 +140,15 @@ config RESET_K210
>>> Say Y if you want to control reset signals provided by this
>>> controller.
>>>
>>> +config RESET_K230
>>> + tristate "Reset controller driver for Canaan Kendryte K230 SoC"
>>> + depends on ARCH_CANAAN || COMPILE_TEST
>>> + depends on OF
>>> + help
>>> + Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
>>> + Say Y if you want to control reset signals provided by this
>>> + controller.
>>> +
>>> config RESET_LANTIQ
>>> bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
>>> default SOC_TYPE_XWAY
>>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>>> index 31f9904d13f9c3a107fc1ee1ec9f9baba016d101..13fe94531bea1eb91268b1804e1321b167815a4b 100644
>>> --- a/drivers/reset/Makefile
>>> +++ b/drivers/reset/Makefile
>>> @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
>>> obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
>>> obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
>>> obj-$(CONFIG_RESET_K210) += reset-k210.o
>>> +obj-$(CONFIG_RESET_K230) += reset-k230.o
>>> obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
>>> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>>> obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
>>> diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..492d2274893675b0ff1967426c8fa9e75aed1791
>>> --- /dev/null
>>> +++ b/drivers/reset/reset-k230.c
>>> @@ -0,0 +1,355 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (C) 2016-2017 Linaro Ltd.
>> Linaro? Are you sure?
> Actually, I kept this from vendor's code.
>
> link: https://github.com/kendryte/k230_sdk/blob/v1.9/src/little/linux/drivers/reset/canaan/reset-k230.c#L19
No reason to keep this, I suggest dropping this line.
>
>>> + * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
>>> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
>>> + */
>>> +
>>> +#include <linux/cleanup.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/io.h>
>>> +#include <linux/iopoll.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/reset-controller.h>
>>> +#include <linux/spinlock.h>
>>> +
>>> +#include <dt-bindings/reset/canaan,k230-rst.h>
>>> +
>>> +/**
>>> + * enum k230_rst_type - K230 reset types
>>> + * @RST_TYPE_CPU0: Reset type for CPU0
>>> + * Automatically clears, has write enable and done bit, active high
>>> + * @RST_TYPE_CPU1: Reset type for CPU1
>>> + * Manually clears, has write enable and done bit, active high
>>> + * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
>>> + * Automatically clears, has write enable, no done bit, active high
>>> + * @RST_TYPE_HW_DONE: Reset type for hardware auto clear
>>> + * Automatically clears, no write enable, has done bit, active high
>>> + * @RST_TYPE_SW_DONE: Reset type for software manual clear
>>> + * Manually clears, no write enable and done bit,
>>> + * active high if ID is RST_SPI2AXI, otherwise active low
>>> + */
>>> +enum k230_rst_type {
>>> + RST_TYPE_CPU0,
>>> + RST_TYPE_CPU1,
>>> + RST_TYPE_FLUSH,
>>> + RST_TYPE_HW_DONE,
>>> + RST_TYPE_SW_DONE,
>>> +};
>>> +
>>> +struct k230_rst_map {
>>> + u32 offset;
>>> + enum k230_rst_type type;
>>> + u32 done;
>>> + u32 reset;
>>> +};
>>> +
>>> +struct k230_rst {
>>> + struct reset_controller_dev rcdev;
>>> + struct device *dev;
>> Why don't usercdev.dev to store the dev, so we can save a pointer.
> Thanks for your reminder, I will store it in rcdev.dev.
>
>>> + void __iomem *base;
>>> + spinlock_t lock;
>>> +};
>> [......]
>>
>> Thanks,
>>
>> Chen
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230
2025-04-19 17:09 ` [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230 Junhui Liu
2025-04-23 3:21 ` Chen Wang
@ 2025-04-23 9:43 ` Philipp Zabel
2025-04-24 7:31 ` Junhui Liu
1 sibling, 1 reply; 10+ messages in thread
From: Philipp Zabel @ 2025-04-23 9:43 UTC (permalink / raw)
To: Junhui Liu, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv
On So, 2025-04-20 at 01:09 +0800, Junhui Liu wrote:
> Add support for the resets on Canaan Kendryte K230 SoC. The driver
> support CPU0, CPU1, L2 cache flush, hardware auto clear and software
> clear resets.
>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>
> ---
> The reset management module in the K230 SoC also provides reset time
> control registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE,
> the time period when reset is applyed/removed but the clock is stopped
> can be set up to 15*0.25 = 3.75 us. For some RST_TYPE_HW_DONE cases, the
> time period can be set up to 255*0.25 = 63.75 us. For RST_TYPE_FLUSH,
> the reset bit will automatically cleared by hardware when flush done.
>
> Although the current reset driver does not support configuration of
> reset time registers, delay has been added to the assert, deassert and
> reset functions to accommodate the longest reset time.
>
> Besides, although some reset types have done bits, the reference manual
> does not explicitly indicate whether the hardware removes reset or the
> clock stop time period has passed when done bits toggle. Therefore, I
> think it is a safer way to keep delay for reset types with done bits.
>
> link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
> ---
> drivers/reset/Kconfig | 9 ++
> drivers/reset/Makefile | 1 +
> drivers/reset/reset-k230.c | 355 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 365 insertions(+)
>
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index 99f6f9784e6865faddf8621ccfca095778c4dc47..248138ffba3bfbf859c74ba1aed7ba2f72819f7a 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -140,6 +140,15 @@ config RESET_K210
> Say Y if you want to control reset signals provided by this
> controller.
>
> +config RESET_K230
> + tristate "Reset controller driver for Canaan Kendryte K230 SoC"
> + depends on ARCH_CANAAN || COMPILE_TEST
> + depends on OF
> + help
> + Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
> + Say Y if you want to control reset signals provided by this
> + controller.
> +
> config RESET_LANTIQ
> bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
> default SOC_TYPE_XWAY
> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> index 31f9904d13f9c3a107fc1ee1ec9f9baba016d101..13fe94531bea1eb91268b1804e1321b167815a4b 100644
> --- a/drivers/reset/Makefile
> +++ b/drivers/reset/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
> obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
> obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
> obj-$(CONFIG_RESET_K210) += reset-k210.o
> +obj-$(CONFIG_RESET_K230) += reset-k230.o
> obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
> diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..492d2274893675b0ff1967426c8fa9e75aed1791
> --- /dev/null
> +++ b/drivers/reset/reset-k230.c
> @@ -0,0 +1,355 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2016-2017 Linaro Ltd.
> + * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
> + */
> +
> +#include <linux/cleanup.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset-controller.h>
> +#include <linux/spinlock.h>
> +
> +#include <dt-bindings/reset/canaan,k230-rst.h>
> +
> +/**
> + * enum k230_rst_type - K230 reset types
> + * @RST_TYPE_CPU0: Reset type for CPU0
> + * Automatically clears, has write enable and done bit, active high
> + * @RST_TYPE_CPU1: Reset type for CPU1
> + * Manually clears, has write enable and done bit, active high
> + * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
> + * Automatically clears, has write enable, no done bit, active high
> + * @RST_TYPE_HW_DONE: Reset type for hardware auto clear
> + * Automatically clears, no write enable, has done bit, active high
> + * @RST_TYPE_SW_DONE: Reset type for software manual clear
> + * Manually clears, no write enable and done bit,
> + * active high if ID is RST_SPI2AXI, otherwise active low
> + */
> +enum k230_rst_type {
> + RST_TYPE_CPU0,
> + RST_TYPE_CPU1,
> + RST_TYPE_FLUSH,
> + RST_TYPE_HW_DONE,
> + RST_TYPE_SW_DONE,
> +};
> +
> +struct k230_rst_map {
> + u32 offset;
> + enum k230_rst_type type;
> + u32 done;
> + u32 reset;
> +};
> +
> +struct k230_rst {
> + struct reset_controller_dev rcdev;
> + struct device *dev;
> + void __iomem *base;
> + spinlock_t lock;
Add a comment, this locks register read-modify-write.
> +};
> +
> +static const struct k230_rst_map k230_resets[] = {
> + [RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) },
> + [RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) },
> + [RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) },
> + [RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) },
> + [RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
> + [RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
> + [RST_HS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) },
> + [RST_HS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) },
The TRM calls these HISYS. Is this shortened to HS on purpose?
[...]
> +static int k230_rst_reset(struct reset_controller_dev *rcdev, unsigned long id)
> +{
> + struct k230_rst *rstc = to_k230_rst(rcdev);
> + const struct k230_rst_map *rmap = &k230_resets[id];
> + u32 reg;
> + int ret = 0;
> +
> + switch (rmap->type) {
> + case RST_TYPE_CPU0:
> + k230_rst_clear_done(rstc, id, true);
> + k230_rst_update(rstc, id, true, true, false);
> + ret = k230_rst_wait_and_clear_done(rstc, id, true);
> +
> + /*
> + * The time period when reset is applied and removed but the
> + * clock is stopped for RST_TYPE_CPU0 can be set up to 7.5us.
> + * Delay 10us to ensure proper reset timing.
> + */
> + udelay(10);
> +
> + break;
> + case RST_TYPE_FLUSH:
> + k230_rst_update(rstc, id, true, true, false);
> +
> + /* Wait flush request bit auto cleared by hardware */
> + ret = readl_poll_timeout(rstc->base + rmap->offset, reg,
> + !(reg & rmap->reset), 10, 1000);
> + if (ret)
> + dev_err(rstc->dev, "Wait for flush done timeout\n");
> +
> + break;
> + case RST_TYPE_HW_DONE:
> + k230_rst_clear_done(rstc, id, false);
> + k230_rst_update(rstc, id, true, false, false);
> + ret = k230_rst_wait_and_clear_done(rstc, id, false);
> +
> + /*
> + * The time period when reset is applied and removed but the
> + * clock is stopped for RST_TYPE_HW_DONE can be set up to
> + * 127.5us. Delay 200us to ensure proper reset timing.
> + */
> + udelay(200);
Consider using usleep_range(), or fsleep().
regards
Philipp
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230
2025-04-23 9:43 ` Philipp Zabel
@ 2025-04-24 7:31 ` Junhui Liu
0 siblings, 0 replies; 10+ messages in thread
From: Junhui Liu @ 2025-04-24 7:31 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel, linux-riscv
Hi Philipp,
Thanks for your review.
On 23/04/2025 11:43, Philipp Zabel wrote:
> On So, 2025-04-20 at 01:09 +0800, Junhui Liu wrote:
>> Add support for the resets on Canaan Kendryte K230 SoC. The driver
>> support CPU0, CPU1, L2 cache flush, hardware auto clear and software
>> clear resets.
>>
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>>
>> ---
>> The reset management module in the K230 SoC also provides reset time
>> control registers. For RST_TYPE_CPU0, RST_TYPE_CPU1 and RST_TYPE_SW_DONE,
>> the time period when reset is applyed/removed but the clock is stopped
>> can be set up to 15*0.25 = 3.75 us. For some RST_TYPE_HW_DONE cases, the
>> time period can be set up to 255*0.25 = 63.75 us. For RST_TYPE_FLUSH,
>> the reset bit will automatically cleared by hardware when flush done.
>>
>> Although the current reset driver does not support configuration of
>> reset time registers, delay has been added to the assert, deassert and
>> reset functions to accommodate the longest reset time.
>>
>> Besides, although some reset types have done bits, the reference manual
>> does not explicitly indicate whether the hardware removes reset or the
>> clock stop time period has passed when done bits toggle. Therefore, I
>> think it is a safer way to keep delay for reset types with done bits.
>>
>> link: https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
>> ---
>> drivers/reset/Kconfig | 9 ++
>> drivers/reset/Makefile | 1 +
>> drivers/reset/reset-k230.c | 355 +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 365 insertions(+)
>>
>> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
>> index 99f6f9784e6865faddf8621ccfca095778c4dc47..248138ffba3bfbf859c74ba1aed7ba2f72819f7a 100644
>> --- a/drivers/reset/Kconfig
>> +++ b/drivers/reset/Kconfig
>> @@ -140,6 +140,15 @@ config RESET_K210
>> Say Y if you want to control reset signals provided by this
>> controller.
>>
>> +config RESET_K230
>> + tristate "Reset controller driver for Canaan Kendryte K230 SoC"
>> + depends on ARCH_CANAAN || COMPILE_TEST
>> + depends on OF
>> + help
>> + Support for the Canaan Kendryte K230 RISC-V SoC reset controller.
>> + Say Y if you want to control reset signals provided by this
>> + controller.
>> +
>> config RESET_LANTIQ
>> bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
>> default SOC_TYPE_XWAY
>> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
>> index 31f9904d13f9c3a107fc1ee1ec9f9baba016d101..13fe94531bea1eb91268b1804e1321b167815a4b 100644
>> --- a/drivers/reset/Makefile
>> +++ b/drivers/reset/Makefile
>> @@ -20,6 +20,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
>> obj-$(CONFIG_RESET_IMX8MP_AUDIOMIX) += reset-imx8mp-audiomix.o
>> obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
>> obj-$(CONFIG_RESET_K210) += reset-k210.o
>> +obj-$(CONFIG_RESET_K230) += reset-k230.o
>> obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
>> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>> obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
>> diff --git a/drivers/reset/reset-k230.c b/drivers/reset/reset-k230.c
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..492d2274893675b0ff1967426c8fa9e75aed1791
>> --- /dev/null
>> +++ b/drivers/reset/reset-k230.c
>> @@ -0,0 +1,355 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (C) 2016-2017 Linaro Ltd.
>> + * Copyright (C) 2022-2024 Canaan Bright Sight Co., Ltd
>> + * Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
>> + */
>> +
>> +#include <linux/cleanup.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset-controller.h>
>> +#include <linux/spinlock.h>
>> +
>> +#include <dt-bindings/reset/canaan,k230-rst.h>
>> +
>> +/**
>> + * enum k230_rst_type - K230 reset types
>> + * @RST_TYPE_CPU0: Reset type for CPU0
>> + * Automatically clears, has write enable and done bit, active high
>> + * @RST_TYPE_CPU1: Reset type for CPU1
>> + * Manually clears, has write enable and done bit, active high
>> + * @RST_TYPE_FLUSH: Reset type for CPU L2 cache flush
>> + * Automatically clears, has write enable, no done bit, active high
>> + * @RST_TYPE_HW_DONE: Reset type for hardware auto clear
>> + * Automatically clears, no write enable, has done bit, active high
>> + * @RST_TYPE_SW_DONE: Reset type for software manual clear
>> + * Manually clears, no write enable and done bit,
>> + * active high if ID is RST_SPI2AXI, otherwise active low
>> + */
>> +enum k230_rst_type {
>> + RST_TYPE_CPU0,
>> + RST_TYPE_CPU1,
>> + RST_TYPE_FLUSH,
>> + RST_TYPE_HW_DONE,
>> + RST_TYPE_SW_DONE,
>> +};
>> +
>> +struct k230_rst_map {
>> + u32 offset;
>> + enum k230_rst_type type;
>> + u32 done;
>> + u32 reset;
>> +};
>> +
>> +struct k230_rst {
>> + struct reset_controller_dev rcdev;
>> + struct device *dev;
>> + void __iomem *base;
>> + spinlock_t lock;
>
> Add a comment, this locks register read-modify-write.
>
>> +};
>> +
>> +static const struct k230_rst_map k230_resets[] = {
>> + [RST_CPU0] = { 0x4, RST_TYPE_CPU0, BIT(12), BIT(0) },
>> + [RST_CPU1] = { 0xc, RST_TYPE_CPU1, BIT(12), BIT(0) },
>> + [RST_CPU0_FLUSH] = { 0x4, RST_TYPE_FLUSH, 0, BIT(4) },
>> + [RST_CPU1_FLUSH] = { 0xc, RST_TYPE_FLUSH, 0, BIT(4) },
>> + [RST_AI] = { 0x14, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
>> + [RST_VPU] = { 0x1c, RST_TYPE_HW_DONE, BIT(31), BIT(0) },
>> + [RST_HS] = { 0x2c, RST_TYPE_HW_DONE, BIT(4), BIT(0) },
>> + [RST_HS_AHB] = { 0x2c, RST_TYPE_HW_DONE, BIT(5), BIT(1) },
>
> The TRM calls these HISYS. Is this shortened to HS on purpose?
>
I kept it with vendor's code, but you're right, HISYS is easier to
understand. I will update this and LS.
> [...]
>
>> +static int k230_rst_reset(struct reset_controller_dev *rcdev, unsigned long id)
>> +{
>> + struct k230_rst *rstc = to_k230_rst(rcdev);
>> + const struct k230_rst_map *rmap = &k230_resets[id];
>> + u32 reg;
>> + int ret = 0;
>> +
>> + switch (rmap->type) {
>> + case RST_TYPE_CPU0:
>> + k230_rst_clear_done(rstc, id, true);
>> + k230_rst_update(rstc, id, true, true, false);
>> + ret = k230_rst_wait_and_clear_done(rstc, id, true);
>> +
>> + /*
>> + * The time period when reset is applied and removed but the
>> + * clock is stopped for RST_TYPE_CPU0 can be set up to 7.5us.
>> + * Delay 10us to ensure proper reset timing.
>> + */
>> + udelay(10);
>> +
>> + break;
>> + case RST_TYPE_FLUSH:
>> + k230_rst_update(rstc, id, true, true, false);
>> +
>> + /* Wait flush request bit auto cleared by hardware */
>> + ret = readl_poll_timeout(rstc->base + rmap->offset, reg,
>> + !(reg & rmap->reset), 10, 1000);
>> + if (ret)
>> + dev_err(rstc->dev, "Wait for flush done timeout\n");
>> +
>> + break;
>> + case RST_TYPE_HW_DONE:
>> + k230_rst_clear_done(rstc, id, false);
>> + k230_rst_update(rstc, id, true, false, false);
>> + ret = k230_rst_wait_and_clear_done(rstc, id, false);
>> +
>> + /*
>> + * The time period when reset is applied and removed but the
>> + * clock is stopped for RST_TYPE_HW_DONE can be set up to
>> + * 127.5us. Delay 200us to ensure proper reset timing.
>> + */
>> + udelay(200);
>
> Consider using usleep_range(), or fsleep().
>
> regards
> Philipp
--
Best regards,
Junhui Liu
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-04-24 7:31 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-04-19 17:09 [PATCH v2 0/2] reset: canaan: add Kendryte K230 reset support Junhui Liu
2025-04-19 17:09 ` [PATCH v2 1/2] dt-bindings: reset: add support for canaan,k230-rst Junhui Liu
2025-04-23 2:21 ` Chen Wang
2025-04-23 5:26 ` Junhui Liu
2025-04-19 17:09 ` [PATCH v2 2/2] reset: canaan: add reset driver for Kendryte K230 Junhui Liu
2025-04-23 3:21 ` Chen Wang
2025-04-23 5:36 ` Junhui Liu
2025-04-23 5:55 ` Chen Wang
2025-04-23 9:43 ` Philipp Zabel
2025-04-24 7:31 ` Junhui Liu
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