[PATCH v2 0/5] Add IAX45 support for RZ/Five SoC

[PATCH v2 0/5] Add IAX45 support for RZ/Five SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found
on the RZ/G2L family of SoCs.

IAX45 performs various interrupt controls including synchronization for the
external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the
built-in peripheral interrupts output by each module. And it notifies the
interrupt to the PLIC.
- Select 32 TINT from 82 GPIOINT.
- Integration of bus error interrupts from system bus.
- Integration of ECC error interrupts from On-chip RAM.
- Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt
  and integrated ECC error interrupt)
- Setting of interrupt detection method. (NMI, IRQ and TINT)
- All interrupts are masked by INTMASK.
- Mask function for NMI, IRQ and TINT

This patch series adds support for IAX45 in the IRQC driver and enables this
on RZ/Five SoC.

v1: https://patchwork.kernel.org/project/linux-renesas-soc/cover/20240129151618.90922-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (5):
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document
    RZ/Five SoC
  irqchip/renesas-rzg2l: Add support for RZ/Five SoC
  riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI
  arm64: dts: renesas: r9a07g043: Move interrupt-parent property to
    common DTSI
  riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt
    properties from ETH0/1 nodes

 .../renesas,rzg2l-irqc.yaml                   |  17 ++-
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi    |   1 +
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   |   4 -
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi   |  75 ++++++++++
 .../boot/dts/renesas/rzfive-smarc-som.dtsi    |  16 --
 drivers/irqchip/irq-renesas-rzg2l.c           | 137 +++++++++++++++++-
 6 files changed, 218 insertions(+), 32 deletions(-)

-- 
2.34.1

[PATCH v2 1/5] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document RZ/Five (R9A07G043F) IRQC bindings. The IRQC block on the RZ/Five
SoC is almost identical to the one found on the RZ/G2L SoC, with the only
difference being that it has additional mask control registers for
NMI/IRQ/TINT.

Hence new compatible string "renesas,r9a07g043f-irqc" is added for RZ/Five
SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- Dropped the checks for interrupts as its already handled
- Added SoC specific compat string
---
 .../renesas,rzg2l-irqc.yaml                     | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index daef4ee06f4e..2a871cbf6f87 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -21,13 +21,16 @@ description: |
 
 properties:
   compatible:
-    items:
-      - enum:
-          - renesas,r9a07g043u-irqc   # RZ/G2UL
-          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
-          - renesas,r9a07g054-irqc    # RZ/V2L
-          - renesas,r9a08g045-irqc    # RZ/G3S
-      - const: renesas,rzg2l-irqc
+    oneOf:
+      - items:
+          - enum:
+              - renesas,r9a07g043u-irqc        # RZ/G2UL
+              - renesas,r9a07g044-irqc         # RZ/G2{L,LC}
+              - renesas,r9a07g054-irqc         # RZ/V2L
+              - renesas,r9a08g045-irqc         # RZ/G3S
+          - const: renesas,rzg2l-irqc
+      - items:
+          - const: renesas,r9a07g043f-irqc     # RZ/Five
 
   '#interrupt-cells':
     description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
-- 
2.34.1

Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC

[Krzysztof Kozlowski]

On 03/04/2024 22:34, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document RZ/Five (R9A07G043F) IRQC bindings. The IRQC block on the RZ/Five
> SoC is almost identical to the one found on the RZ/G2L SoC, with the only
> difference being that it has additional mask control registers for
> NMI/IRQ/TINT.
> 
> Hence new compatible string "renesas,r9a07g043f-irqc" is added for RZ/Five
> SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Dropped the checks for interrupts as its already handled
> - Added SoC specific compat string
> ---
>  .../renesas,rzg2l-irqc.yaml                     | 17 ++++++++++-------
>  1 file changed, 10 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index daef4ee06f4e..2a871cbf6f87 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -21,13 +21,16 @@ description: |
>  
>  properties:
>    compatible:
> -    items:
> -      - enum:
> -          - renesas,r9a07g043u-irqc   # RZ/G2UL
> -          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
> -          - renesas,r9a07g054-irqc    # RZ/V2L
> -          - renesas,r9a08g045-irqc    # RZ/G3S
> -      - const: renesas,rzg2l-irqc
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,r9a07g043u-irqc        # RZ/G2UL
> +              - renesas,r9a07g044-irqc         # RZ/G2{L,LC}
> +              - renesas,r9a07g054-irqc         # RZ/V2L
> +              - renesas,r9a08g045-irqc         # RZ/G3S
> +          - const: renesas,rzg2l-irqc
> +      - items:

This is just const, no need for items.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 1/5] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/Five SoC

[Geert Uytterhoeven]

On Wed, Apr 3, 2024 at 10:36 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document RZ/Five (R9A07G043F) IRQC bindings. The IRQC block on the RZ/Five
> SoC is almost identical to the one found on the RZ/G2L SoC, with the only
> difference being that it has additional mask control registers for
> NMI/IRQ/TINT.
>
> Hence new compatible string "renesas,r9a07g043f-irqc" is added for RZ/Five
> SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Dropped the checks for interrupts as its already handled
> - Added SoC specific compat string

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared
to the RZ/G2L (family) SoC.

Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC
controller driver. Two new registers, IMSK and TMSK, are defined to
handle masking on RZ/Five SoC. The implementation utilizes a new data
structure, `struct rzg2l_irqc_data`, to determine mask support for a
specific controller instance.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- Added IRQCHIP_MATCH() for RZ/Five
- Retaining a copy of OF data in priv
- Rebased the changes
---
 drivers/irqchip/irq-renesas-rzg2l.c | 137 +++++++++++++++++++++++++++-
 1 file changed, 132 insertions(+), 5 deletions(-)

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index f6484bf15e0b..6fa8d65605dc 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -37,6 +37,8 @@
 #define TSSEL_SHIFT(n)			(8 * (n))
 #define TSSEL_MASK			GENMASK(7, 0)
 #define IRQ_MASK			0x3
+#define IMSK				0x10010
+#define TMSK				0x10020
 
 #define TSSR_OFFSET(n)			((n) % 4)
 #define TSSR_INDEX(n)			((n) / 4)
@@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
 	u32	titsr[2];
 };
 
+/**
+ * struct rzg2l_irqc_of_data - OF data structure
+ * @mask_supported: Indicates if mask registers are available
+ */
+struct rzg2l_irqc_of_data {
+	bool	mask_supported;
+};
+
 /**
  * struct rzg2l_irqc_priv - IRQ controller private data structure
  * @base:	Controller's base address
+ * @data:	OF data pointer
  * @fwspec:	IRQ firmware specific data
  * @lock:	Lock to serialize access to hardware registers
  * @cache:	Registers cache for suspend/resume
  */
 static struct rzg2l_irqc_priv {
 	void __iomem			*base;
+	const struct rzg2l_irqc_of_data	*data;
 	struct irq_fwspec		fwspec[IRQC_NUM_IRQ];
 	raw_spinlock_t			lock;
 	struct rzg2l_irqc_reg_cache	cache;
@@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
 	irq_chip_eoi_parent(d);
 }
 
+static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
+					  unsigned int hwirq)
+{
+	u32 imsk = readl_relaxed(priv->base + IMSK);
+	u32 bit = BIT(hwirq - IRQC_IRQ_START);
+
+	writel_relaxed(imsk | bit, priv->base + IMSK);
+}
+
+static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
+					    unsigned int hwirq)
+{
+	u32 imsk = readl_relaxed(priv->base + IMSK);
+	u32 bit = BIT(hwirq - IRQC_IRQ_START);
+
+	writel_relaxed(imsk & ~bit, priv->base + IMSK);
+}
+
+static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
+					   unsigned int hwirq)
+{
+	u32 tmsk = readl_relaxed(priv->base + TMSK);
+	u32 bit = BIT(hwirq - IRQC_TINT_START);
+
+	writel_relaxed(tmsk | bit, priv->base + TMSK);
+}
+
+static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
+					     unsigned int hwirq)
+{
+	u32 tmsk = readl_relaxed(priv->base + TMSK);
+	u32 bit = BIT(hwirq - IRQC_TINT_START);
+
+	writel_relaxed(tmsk & ~bit, priv->base + TMSK);
+}
+
+/* Must be called while priv->lock is held */
+static void rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
+{
+	if (!priv->data->mask_supported)
+		return;
+
+	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
+		rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
+	else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
+		rzg2l_irqc_mask_tint_interrupt(priv, hwirq);
+}
+
+static void rzg2l_irqc_mask(struct irq_data *d)
+{
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
+
+	raw_spin_lock(&priv->lock);
+	rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
+	raw_spin_unlock(&priv->lock);
+	irq_chip_mask_parent(d);
+}
+
+/* Must be called while priv->lock is held */
+static void rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
+{
+	if (!priv->data->mask_supported)
+		return;
+
+	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
+		rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
+	else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
+		rzg2l_irqc_unmask_tint_interrupt(priv, hwirq);
+}
+
+static void rzg2l_irqc_unmask(struct irq_data *d)
+{
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
+
+	raw_spin_lock(&priv->lock);
+	rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
+	raw_spin_unlock(&priv->lock);
+	irq_chip_unmask_parent(d);
+}
+
 static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
 {
+	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 	unsigned int hw_irq = irqd_to_hwirq(d);
 
 	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
-		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
 		u32 offset = hw_irq - IRQC_TINT_START;
 		u32 tssr_offset = TSSR_OFFSET(offset);
 		u8 tssr_index = TSSR_INDEX(offset);
 		u32 reg;
 
 		raw_spin_lock(&priv->lock);
+		if (enable)
+			rzg2l_irqc_unmask_once(priv, hw_irq);
+		else
+			rzg2l_irqc_mask_once(priv, hw_irq);
 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
 		if (enable)
 			reg |= TIEN << TSSEL_SHIFT(tssr_offset);
@@ -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
 			reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
 		writel_relaxed(reg, priv->base + TSSR(tssr_index));
 		raw_spin_unlock(&priv->lock);
+	} else {
+		raw_spin_lock(&priv->lock);
+		if (enable)
+			rzg2l_irqc_unmask_once(priv, hw_irq);
+		else
+			rzg2l_irqc_mask_once(priv, hw_irq);
+		raw_spin_unlock(&priv->lock);
 	}
 }
 
@@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops = {
 static const struct irq_chip irqc_chip = {
 	.name			= "rzg2l-irqc",
 	.irq_eoi		= rzg2l_irqc_eoi,
-	.irq_mask		= irq_chip_mask_parent,
-	.irq_unmask		= irq_chip_unmask_parent,
+	.irq_mask		= rzg2l_irqc_mask,
+	.irq_unmask		= rzg2l_irqc_unmask,
 	.irq_disable		= rzg2l_irqc_irq_disable,
 	.irq_enable		= rzg2l_irqc_irq_enable,
 	.irq_get_irqchip_state	= irq_chip_get_parent_state,
@@ -401,7 +504,16 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
 	return 0;
 }
 
-static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
+static const struct rzg2l_irqc_of_data rzg2l_irqc_mask_supported_data = {
+	.mask_supported = true,
+};
+
+static const struct rzg2l_irqc_of_data rzg2l_irqc_default_data = {
+	.mask_supported = false,
+};
+
+static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent,
+			   const struct rzg2l_irqc_of_data *of_data)
 {
 	struct irq_domain *irq_domain, *parent_domain;
 	struct platform_device *pdev;
@@ -422,6 +534,8 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
 	if (!rzg2l_irqc_data)
 		return -ENOMEM;
 
+	rzg2l_irqc_data->data = of_data;
+
 	rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
 	if (IS_ERR(rzg2l_irqc_data->base))
 		return PTR_ERR(rzg2l_irqc_data->base);
@@ -472,8 +586,21 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
 	return ret;
 }
 
+static int __init rzg2l_irqc_default_init(struct device_node *node,
+					  struct device_node *parent)
+{
+	return rzg2l_irqc_init(node, parent, &rzg2l_irqc_default_data);
+}
+
+static int __init rzg2l_irqc_mask_supported_init(struct device_node *node,
+						 struct device_node *parent)
+{
+	return rzg2l_irqc_init(node, parent, &rzg2l_irqc_mask_supported_data);
+}
+
 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
-IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
+IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_default_init)
+IRQCHIP_MATCH("renesas,r9a07g043f-irqc", rzg2l_irqc_mask_supported_init)
 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
-- 
2.34.1

RE: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Biju Das]

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Wednesday, April 3, 2024 9:35 PM
> Subject: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared to the RZ/G2L (family)
> SoC.
> 
> Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC controller driver. Two new
> registers, IMSK and TMSK, are defined to handle masking on RZ/Five SoC. The implementation utilizes
> a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a specific controller
> instance.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Added IRQCHIP_MATCH() for RZ/Five
> - Retaining a copy of OF data in priv
> - Rebased the changes
> ---
>  drivers/irqchip/irq-renesas-rzg2l.c | 137 +++++++++++++++++++++++++++-
>  1 file changed, 132 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> index f6484bf15e0b..6fa8d65605dc 100644
> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -37,6 +37,8 @@
>  #define TSSEL_SHIFT(n)			(8 * (n))
>  #define TSSEL_MASK			GENMASK(7, 0)
>  #define IRQ_MASK			0x3
> +#define IMSK				0x10010
> +#define TMSK				0x10020
> 
>  #define TSSR_OFFSET(n)			((n) % 4)
>  #define TSSR_INDEX(n)			((n) / 4)
> @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
>  	u32	titsr[2];
>  };
> 
> +/**
> + * struct rzg2l_irqc_of_data - OF data structure
> + * @mask_supported: Indicates if mask registers are available  */
> +struct rzg2l_irqc_of_data {
> +	bool	mask_supported;
> +};
> +
>  /**
>   * struct rzg2l_irqc_priv - IRQ controller private data structure
>   * @base:	Controller's base address
> + * @data:	OF data pointer
>   * @fwspec:	IRQ firmware specific data
>   * @lock:	Lock to serialize access to hardware registers
>   * @cache:	Registers cache for suspend/resume
>   */
>  static struct rzg2l_irqc_priv {
>  	void __iomem			*base;
> +	const struct rzg2l_irqc_of_data	*data;
>  	struct irq_fwspec		fwspec[IRQC_NUM_IRQ];
>  	raw_spinlock_t			lock;
>  	struct rzg2l_irqc_reg_cache	cache;
> @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
>  	irq_chip_eoi_parent(d);
>  }
> 
> +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> +					  unsigned int hwirq)
> +{
> +	u32 imsk = readl_relaxed(priv->base + IMSK);
> +	u32 bit = BIT(hwirq - IRQC_IRQ_START);
> +
> +	writel_relaxed(imsk | bit, priv->base + IMSK); }
> +
> +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> +					    unsigned int hwirq)
> +{
> +	u32 imsk = readl_relaxed(priv->base + IMSK);
> +	u32 bit = BIT(hwirq - IRQC_IRQ_START);
> +
> +	writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> +
> +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> +					   unsigned int hwirq)
> +{
> +	u32 tmsk = readl_relaxed(priv->base + TMSK);
> +	u32 bit = BIT(hwirq - IRQC_TINT_START);
> +
> +	writel_relaxed(tmsk | bit, priv->base + TMSK); }
> +
> +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> +					     unsigned int hwirq)
> +{
> +	u32 tmsk = readl_relaxed(priv->base + TMSK);
> +	u32 bit = BIT(hwirq - IRQC_TINT_START);
> +
> +	writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> +
> +/* Must be called while priv->lock is held */ static void
> +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> +{
> +	if (!priv->data->mask_supported)
> +		return;
> +
> +	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> +		rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> +	else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> +		rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> +
> +static void rzg2l_irqc_mask(struct irq_data *d) {
> +	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> +
> +	raw_spin_lock(&priv->lock);
> +	rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> +	raw_spin_unlock(&priv->lock);
> +	irq_chip_mask_parent(d);
> +}
> +
> +/* Must be called while priv->lock is held */ static void
> +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> +hwirq) {
> +	if (!priv->data->mask_supported)
> +		return;
> +
> +	if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> +		rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> +	else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> +		rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> +
> +static void rzg2l_irqc_unmask(struct irq_data *d) {
> +	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> +
> +	raw_spin_lock(&priv->lock);
> +	rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> +	raw_spin_unlock(&priv->lock);
> +	irq_chip_unmask_parent(d);
> +}
> +
>  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)  {
> +	struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
>  	unsigned int hw_irq = irqd_to_hwirq(d);
> 
>  	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> -		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
>  		u32 offset = hw_irq - IRQC_TINT_START;
>  		u32 tssr_offset = TSSR_OFFSET(offset);
>  		u8 tssr_index = TSSR_INDEX(offset);
>  		u32 reg;
> 
>  		raw_spin_lock(&priv->lock);
> +		if (enable)
> +			rzg2l_irqc_unmask_once(priv, hw_irq);
> +		else
> +			rzg2l_irqc_mask_once(priv, hw_irq);
>  		reg = readl_relaxed(priv->base + TSSR(tssr_index));
>  		if (enable)
>  			reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@ -157,6 +253,13 @@ static void
> rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
>  			reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
>  		writel_relaxed(reg, priv->base + TSSR(tssr_index));
>  		raw_spin_unlock(&priv->lock);
> +	} else {
> +		raw_spin_lock(&priv->lock);
> +		if (enable)
> +			rzg2l_irqc_unmask_once(priv, hw_irq);
> +		else
> +			rzg2l_irqc_mask_once(priv, hw_irq);
> +		raw_spin_unlock(&priv->lock);
>  	}
>  }
> 
> @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops = {  static const struct
> irq_chip irqc_chip = {
>  	.name			= "rzg2l-irqc",
>  	.irq_eoi		= rzg2l_irqc_eoi,
> -	.irq_mask		= irq_chip_mask_parent,
> -	.irq_unmask		= irq_chip_unmask_parent,
> +	.irq_mask		= rzg2l_irqc_mask,
> +	.irq_unmask		= rzg2l_irqc_unmask,

I feel this will be clean, if we have 

static const struct irq_chip rzg2l_irqc_chip = {
	.name			= "rzg2l-irqc",
	...
	.irq_mask		= irq_chip_mask_parent,
	.irq_unmask		= irq_chip_unmask_parent,
	....
};

static const struct irq_chip rzfive_irqc_chip = {
	.name			= "rzfive-irqc",
	...
	.irq_mask		= rzfive_irqc_mask,
	.irq_unmask		= rzfive_irqc_unmask,
	....
};

And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see below

return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip);
return rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);


>  	.irq_disable		= rzg2l_irqc_irq_disable,
>  	.irq_enable		= rzg2l_irqc_irq_enable,
>  	.irq_get_irqchip_state	= irq_chip_get_parent_state,
> @@ -401,7 +504,16 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
>  	return 0;
>  }
> 
> -static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
> +static const struct rzg2l_irqc_of_data rzg2l_irqc_mask_supported_data = {
> +	.mask_supported = true,
> +};
> +
> +static const struct rzg2l_irqc_of_data rzg2l_irqc_default_data = {
> +	.mask_supported = false,
> +};
> +
> +static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent,
> +			   const struct rzg2l_irqc_of_data *of_data)

Maybe rename this as rzg2l_irqc_init_helper()
>  {
>  	struct irq_domain *irq_domain, *parent_domain;
>  	struct platform_device *pdev;
> @@ -422,6 +534,8 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node
> *parent)
>  	if (!rzg2l_irqc_data)
>  		return -ENOMEM;
> 
> +	rzg2l_irqc_data->data = of_data;
> +
>  	rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
>  	if (IS_ERR(rzg2l_irqc_data->base))
>  		return PTR_ERR(rzg2l_irqc_data->base); @@ -472,8 +586,21 @@ static int
> rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
>  	return ret;
>  }
> 
> +static int __init rzg2l_irqc_default_init(struct device_node *node,
> +					  struct device_node *parent)
> +{
> +	return rzg2l_irqc_init(node, parent, &rzg2l_irqc_default_data); }
> +
> +static int __init rzg2l_irqc_mask_supported_init(struct device_node *node,
> +						 struct device_node *parent)
> +{
> +	return rzg2l_irqc_init(node, parent, &rzg2l_irqc_mask_supported_data);
> +}
> +
>  IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
> -IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
Retain this name

> +IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_default_init)
> +IRQCHIP_MATCH("renesas,r9a07g043f-irqc",
> +rzg2l_irqc_mask_supported_init)
Maybe rename this as rzfive_irqc_init ??

Cheers,
Biju

>  IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
>  MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
>  MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
> --
> 2.34.1
> 

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Lad, Prabhakar]

Hi Biju,

Thank you for the review.

On Thu, Apr 4, 2024 at 8:44 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Wednesday, April 3, 2024 9:35 PM
> > Subject: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared to the RZ/G2L (family)
> > SoC.
> >
> > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC controller driver. Two new
> > registers, IMSK and TMSK, are defined to handle masking on RZ/Five SoC. The implementation utilizes
> > a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a specific controller
> > instance.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - Added IRQCHIP_MATCH() for RZ/Five
> > - Retaining a copy of OF data in priv
> > - Rebased the changes
> > ---
> >  drivers/irqchip/irq-renesas-rzg2l.c | 137 +++++++++++++++++++++++++++-
> >  1 file changed, 132 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
> > index f6484bf15e0b..6fa8d65605dc 100644
> > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > @@ -37,6 +37,8 @@
> >  #define TSSEL_SHIFT(n)                       (8 * (n))
> >  #define TSSEL_MASK                   GENMASK(7, 0)
> >  #define IRQ_MASK                     0x3
> > +#define IMSK                         0x10010
> > +#define TMSK                         0x10020
> >
> >  #define TSSR_OFFSET(n)                       ((n) % 4)
> >  #define TSSR_INDEX(n)                        ((n) / 4)
> > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> >       u32     titsr[2];
> >  };
> >
> > +/**
> > + * struct rzg2l_irqc_of_data - OF data structure
> > + * @mask_supported: Indicates if mask registers are available  */
> > +struct rzg2l_irqc_of_data {
> > +     bool    mask_supported;
> > +};
> > +
> >  /**
> >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> >   * @base:    Controller's base address
> > + * @data:    OF data pointer
> >   * @fwspec:  IRQ firmware specific data
> >   * @lock:    Lock to serialize access to hardware registers
> >   * @cache:   Registers cache for suspend/resume
> >   */
> >  static struct rzg2l_irqc_priv {
> >       void __iomem                    *base;
> > +     const struct rzg2l_irqc_of_data *data;
> >       struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> >       raw_spinlock_t                  lock;
> >       struct rzg2l_irqc_reg_cache     cache;
> > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> >       irq_chip_eoi_parent(d);
> >  }
> >
> > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                       unsigned int hwirq)
> > +{
> > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > +     writel_relaxed(imsk | bit, priv->base + IMSK); }
> > +
> > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                         unsigned int hwirq)
> > +{
> > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > +     writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > +
> > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                        unsigned int hwirq)
> > +{
> > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > +
> > +     writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > +
> > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                          unsigned int hwirq)
> > +{
> > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > +
> > +     writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > +
> > +/* Must be called while priv->lock is held */ static void
> > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> > +{
> > +     if (!priv->data->mask_supported)
> > +             return;
> > +
> > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > +             rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > +             rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > +
> > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > +
> > +     raw_spin_lock(&priv->lock);
> > +     rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > +     raw_spin_unlock(&priv->lock);
> > +     irq_chip_mask_parent(d);
> > +}
> > +
> > +/* Must be called while priv->lock is held */ static void
> > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > +hwirq) {
> > +     if (!priv->data->mask_supported)
> > +             return;
> > +
> > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > +             rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > +             rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > +
> > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > +
> > +     raw_spin_lock(&priv->lock);
> > +     rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > +     raw_spin_unlock(&priv->lock);
> > +     irq_chip_unmask_parent(d);
> > +}
> > +
> >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)  {
> > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> >       unsigned int hw_irq = irqd_to_hwirq(d);
> >
> >       if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > -             struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> >               u32 offset = hw_irq - IRQC_TINT_START;
> >               u32 tssr_offset = TSSR_OFFSET(offset);
> >               u8 tssr_index = TSSR_INDEX(offset);
> >               u32 reg;
> >
> >               raw_spin_lock(&priv->lock);
> > +             if (enable)
> > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > +             else
> > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> >               reg = readl_relaxed(priv->base + TSSR(tssr_index));
> >               if (enable)
> >                       reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@ -157,6 +253,13 @@ static void
> > rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> >                       reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> >               writel_relaxed(reg, priv->base + TSSR(tssr_index));
> >               raw_spin_unlock(&priv->lock);
> > +     } else {
> > +             raw_spin_lock(&priv->lock);
> > +             if (enable)
> > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > +             else
> > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > +             raw_spin_unlock(&priv->lock);
> >       }
> >  }
> >
> > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops = {  static const struct
> > irq_chip irqc_chip = {
> >       .name                   = "rzg2l-irqc",
> >       .irq_eoi                = rzg2l_irqc_eoi,
> > -     .irq_mask               = irq_chip_mask_parent,
> > -     .irq_unmask             = irq_chip_unmask_parent,
> > +     .irq_mask               = rzg2l_irqc_mask,
> > +     .irq_unmask             = rzg2l_irqc_unmask,
>
> I feel this will be clean, if we have
>
> static const struct irq_chip rzg2l_irqc_chip = {
>         .name                   = "rzg2l-irqc",
>         ...
>         .irq_mask               = irq_chip_mask_parent,
>         .irq_unmask             = irq_chip_unmask_parent,
>         ....
> };
>
> static const struct irq_chip rzfive_irqc_chip = {
>         .name                   = "rzfive-irqc",
>         ...
>         .irq_mask               = rzfive_irqc_mask,
>         .irq_unmask             = rzfive_irqc_unmask,
>         ....
> };
>
> And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see below
>
> return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip);
> return rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
>
If we do the above we are stuck with "struct irq_chip" as data, for
further upcoming SoCs (for example RZ/V2H) which have more features we
need to pass custom data to handle these features.

>
> >       .irq_disable            = rzg2l_irqc_irq_disable,
> >       .irq_enable             = rzg2l_irqc_irq_enable,
> >       .irq_get_irqchip_state  = irq_chip_get_parent_state,
> > @@ -401,7 +504,16 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
> >       return 0;
> >  }
> >
> > -static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
> > +static const struct rzg2l_irqc_of_data rzg2l_irqc_mask_supported_data = {
> > +     .mask_supported = true,
> > +};
> > +
> > +static const struct rzg2l_irqc_of_data rzg2l_irqc_default_data = {
> > +     .mask_supported = false,
> > +};
> > +
> > +static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent,
> > +                        const struct rzg2l_irqc_of_data *of_data)
>
> Maybe rename this as rzg2l_irqc_init_helper()
OK.

> >  {
> >       struct irq_domain *irq_domain, *parent_domain;
> >       struct platform_device *pdev;
> > @@ -422,6 +534,8 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node
> > *parent)
> >       if (!rzg2l_irqc_data)
> >               return -ENOMEM;
> >
> > +     rzg2l_irqc_data->data = of_data;
> > +
> >       rzg2l_irqc_data->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
> >       if (IS_ERR(rzg2l_irqc_data->base))
> >               return PTR_ERR(rzg2l_irqc_data->base); @@ -472,8 +586,21 @@ static int
> > rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
> >       return ret;
> >  }
> >
> > +static int __init rzg2l_irqc_default_init(struct device_node *node,
> > +                                       struct device_node *parent)
> > +{
> > +     return rzg2l_irqc_init(node, parent, &rzg2l_irqc_default_data); }
> > +
> > +static int __init rzg2l_irqc_mask_supported_init(struct device_node *node,
> > +                                              struct device_node *parent)
> > +{
> > +     return rzg2l_irqc_init(node, parent, &rzg2l_irqc_mask_supported_data);
> > +}
> > +
> >  IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
> > -IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
> Retain this name
>
OK.

> > +IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_default_init)
> > +IRQCHIP_MATCH("renesas,r9a07g043f-irqc",
> > +rzg2l_irqc_mask_supported_init)
> Maybe rename this as rzfive_irqc_init ??
>
OK.

Cheers,
Prabhakar

RE: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Biju Das]

Hi Lad, Prabhakar,

> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Thursday, April 4, 2024 2:27 PM
> Subject: Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
> 
> Hi Biju,
> 
> Thank you for the review.
> 
> On Thu, Apr 4, 2024 at 8:44 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > Thanks for the patch.
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Wednesday, April 3, 2024 9:35 PM
> > > Subject: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for
> > > RZ/Five SoC
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as
> > > compared to the RZ/G2L (family) SoC.
> > >
> > > Introduce masking/unmasking support for IRQ and TINT interrupts in
> > > IRQC controller driver. Two new registers, IMSK and TMSK, are
> > > defined to handle masking on RZ/Five SoC. The implementation
> > > utilizes a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a
> specific controller instance.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - Added IRQCHIP_MATCH() for RZ/Five
> > > - Retaining a copy of OF data in priv
> > > - Rebased the changes
> > > ---
> > >  drivers/irqchip/irq-renesas-rzg2l.c | 137
> > > +++++++++++++++++++++++++++-
> > >  1 file changed, 132 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c
> > > b/drivers/irqchip/irq-renesas-rzg2l.c
> > > index f6484bf15e0b..6fa8d65605dc 100644
> > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > @@ -37,6 +37,8 @@
> > >  #define TSSEL_SHIFT(n)                       (8 * (n))
> > >  #define TSSEL_MASK                   GENMASK(7, 0)
> > >  #define IRQ_MASK                     0x3
> > > +#define IMSK                         0x10010
> > > +#define TMSK                         0x10020
> > >
> > >  #define TSSR_OFFSET(n)                       ((n) % 4)
> > >  #define TSSR_INDEX(n)                        ((n) / 4)
> > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > >       u32     titsr[2];
> > >  };
> > >
> > > +/**
> > > + * struct rzg2l_irqc_of_data - OF data structure
> > > + * @mask_supported: Indicates if mask registers are available  */
> > > +struct rzg2l_irqc_of_data {
> > > +     bool    mask_supported;
> > > +};
> > > +
> > >  /**
> > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > >   * @base:    Controller's base address
> > > + * @data:    OF data pointer
> > >   * @fwspec:  IRQ firmware specific data
> > >   * @lock:    Lock to serialize access to hardware registers
> > >   * @cache:   Registers cache for suspend/resume
> > >   */
> > >  static struct rzg2l_irqc_priv {
> > >       void __iomem                    *base;
> > > +     const struct rzg2l_irqc_of_data *data;
> > >       struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> > >       raw_spinlock_t                  lock;
> > >       struct rzg2l_irqc_reg_cache     cache;
> > > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> > >       irq_chip_eoi_parent(d);
> > >  }
> > >
> > > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > +                                       unsigned int hwirq) {
> > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > +
> > > +     writel_relaxed(imsk | bit, priv->base + IMSK); }
> > > +
> > > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > +                                         unsigned int hwirq) {
> > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > +
> > > +     writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > > +
> > > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > +                                        unsigned int hwirq) {
> > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > +
> > > +     writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > > +
> > > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > +                                          unsigned int hwirq) {
> > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > +
> > > +     writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > > +
> > > +/* Must be called while priv->lock is held */ static void
> > > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > +hwirq) {
> > > +     if (!priv->data->mask_supported)
> > > +             return;
> > > +
> > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > +             rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > +             rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > > +
> > > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > +
> > > +     raw_spin_lock(&priv->lock);
> > > +     rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > > +     raw_spin_unlock(&priv->lock);
> > > +     irq_chip_mask_parent(d);
> > > +}
> > > +
> > > +/* Must be called while priv->lock is held */ static void
> > > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > +hwirq) {
> > > +     if (!priv->data->mask_supported)
> > > +             return;
> > > +
> > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > +             rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > +             rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > > +
> > > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > +
> > > +     raw_spin_lock(&priv->lock);
> > > +     rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > > +     raw_spin_unlock(&priv->lock);
> > > +     irq_chip_unmask_parent(d);
> > > +}
> > > +
> > >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool
> > > enable)  {
> > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > >       unsigned int hw_irq = irqd_to_hwirq(d);
> > >
> > >       if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > > -             struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > >               u32 offset = hw_irq - IRQC_TINT_START;
> > >               u32 tssr_offset = TSSR_OFFSET(offset);
> > >               u8 tssr_index = TSSR_INDEX(offset);
> > >               u32 reg;
> > >
> > >               raw_spin_lock(&priv->lock);
> > > +             if (enable)
> > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > +             else
> > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > >               reg = readl_relaxed(priv->base + TSSR(tssr_index));
> > >               if (enable)
> > >                       reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@
> > > -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> > >                       reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> > >               writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > >               raw_spin_unlock(&priv->lock);
> > > +     } else {
> > > +             raw_spin_lock(&priv->lock);
> > > +             if (enable)
> > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > +             else
> > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > +             raw_spin_unlock(&priv->lock);
> > >       }
> > >  }
> > >
> > > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops
> > > = {  static const struct irq_chip irqc_chip = {
> > >       .name                   = "rzg2l-irqc",
> > >       .irq_eoi                = rzg2l_irqc_eoi,
> > > -     .irq_mask               = irq_chip_mask_parent,
> > > -     .irq_unmask             = irq_chip_unmask_parent,
> > > +     .irq_mask               = rzg2l_irqc_mask,
> > > +     .irq_unmask             = rzg2l_irqc_unmask,
> >
> > I feel this will be clean, if we have
> >
> > static const struct irq_chip rzg2l_irqc_chip = {
> >         .name                   = "rzg2l-irqc",
> >         ...
> >         .irq_mask               = irq_chip_mask_parent,
> >         .irq_unmask             = irq_chip_unmask_parent,
> >         ....
> > };
> >
> > static const struct irq_chip rzfive_irqc_chip = {
> >         .name                   = "rzfive-irqc",
> >         ...
> >         .irq_mask               = rzfive_irqc_mask,
> >         .irq_unmask             = rzfive_irqc_unmask,
> >         ....
> > };
> >
> > And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see
> > below
> >
> > return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip); return
> > rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
> >
> If we do the above we are stuck with "struct irq_chip" as data, for further upcoming SoCs (for
> example RZ/V2H) which have more features we need to pass custom data to handle these features.

That time device data can be extended like below

struct rz_g2l_irq_chip {
	struct irq_chip;
	void *data; /* custom data */
}

Cheers,
Biju

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Lad, Prabhakar]

On Thu, Apr 4, 2024 at 2:31 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Lad, Prabhakar,
>
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Thursday, April 4, 2024 2:27 PM
> > Subject: Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC
> >
> > Hi Biju,
> >
> > Thank you for the review.
> >
> > On Thu, Apr 4, 2024 at 8:44 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > Thanks for the patch.
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Wednesday, April 3, 2024 9:35 PM
> > > > Subject: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for
> > > > RZ/Five SoC
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as
> > > > compared to the RZ/G2L (family) SoC.
> > > >
> > > > Introduce masking/unmasking support for IRQ and TINT interrupts in
> > > > IRQC controller driver. Two new registers, IMSK and TMSK, are
> > > > defined to handle masking on RZ/Five SoC. The implementation
> > > > utilizes a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a
> > specific controller instance.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > - Added IRQCHIP_MATCH() for RZ/Five
> > > > - Retaining a copy of OF data in priv
> > > > - Rebased the changes
> > > > ---
> > > >  drivers/irqchip/irq-renesas-rzg2l.c | 137
> > > > +++++++++++++++++++++++++++-
> > > >  1 file changed, 132 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > index f6484bf15e0b..6fa8d65605dc 100644
> > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > @@ -37,6 +37,8 @@
> > > >  #define TSSEL_SHIFT(n)                       (8 * (n))
> > > >  #define TSSEL_MASK                   GENMASK(7, 0)
> > > >  #define IRQ_MASK                     0x3
> > > > +#define IMSK                         0x10010
> > > > +#define TMSK                         0x10020
> > > >
> > > >  #define TSSR_OFFSET(n)                       ((n) % 4)
> > > >  #define TSSR_INDEX(n)                        ((n) / 4)
> > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > > >       u32     titsr[2];
> > > >  };
> > > >
> > > > +/**
> > > > + * struct rzg2l_irqc_of_data - OF data structure
> > > > + * @mask_supported: Indicates if mask registers are available  */
> > > > +struct rzg2l_irqc_of_data {
> > > > +     bool    mask_supported;
> > > > +};
> > > > +
> > > >  /**
> > > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > > >   * @base:    Controller's base address
> > > > + * @data:    OF data pointer
> > > >   * @fwspec:  IRQ firmware specific data
> > > >   * @lock:    Lock to serialize access to hardware registers
> > > >   * @cache:   Registers cache for suspend/resume
> > > >   */
> > > >  static struct rzg2l_irqc_priv {
> > > >       void __iomem                    *base;
> > > > +     const struct rzg2l_irqc_of_data *data;
> > > >       struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> > > >       raw_spinlock_t                  lock;
> > > >       struct rzg2l_irqc_reg_cache     cache;
> > > > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> > > >       irq_chip_eoi_parent(d);
> > > >  }
> > > >
> > > > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > > +                                       unsigned int hwirq) {
> > > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > > +
> > > > +     writel_relaxed(imsk | bit, priv->base + IMSK); }
> > > > +
> > > > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > > +                                         unsigned int hwirq) {
> > > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > > +
> > > > +     writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > > > +
> > > > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > > +                                        unsigned int hwirq) {
> > > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > > +
> > > > +     writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > > > +
> > > > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > > +                                          unsigned int hwirq) {
> > > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > > +
> > > > +     writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > > > +
> > > > +/* Must be called while priv->lock is held */ static void
> > > > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > > +hwirq) {
> > > > +     if (!priv->data->mask_supported)
> > > > +             return;
> > > > +
> > > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > > +             rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > > +             rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > > > +
> > > > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > +
> > > > +     raw_spin_lock(&priv->lock);
> > > > +     rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > > > +     raw_spin_unlock(&priv->lock);
> > > > +     irq_chip_mask_parent(d);
> > > > +}
> > > > +
> > > > +/* Must be called while priv->lock is held */ static void
> > > > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > > +hwirq) {
> > > > +     if (!priv->data->mask_supported)
> > > > +             return;
> > > > +
> > > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > > +             rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > > +             rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > > > +
> > > > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > +
> > > > +     raw_spin_lock(&priv->lock);
> > > > +     rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > > > +     raw_spin_unlock(&priv->lock);
> > > > +     irq_chip_unmask_parent(d);
> > > > +}
> > > > +
> > > >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool
> > > > enable)  {
> > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > >       unsigned int hw_irq = irqd_to_hwirq(d);
> > > >
> > > >       if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > > > -             struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > >               u32 offset = hw_irq - IRQC_TINT_START;
> > > >               u32 tssr_offset = TSSR_OFFSET(offset);
> > > >               u8 tssr_index = TSSR_INDEX(offset);
> > > >               u32 reg;
> > > >
> > > >               raw_spin_lock(&priv->lock);
> > > > +             if (enable)
> > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > +             else
> > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > >               reg = readl_relaxed(priv->base + TSSR(tssr_index));
> > > >               if (enable)
> > > >                       reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@
> > > > -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> > > >                       reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> > > >               writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > > >               raw_spin_unlock(&priv->lock);
> > > > +     } else {
> > > > +             raw_spin_lock(&priv->lock);
> > > > +             if (enable)
> > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > +             else
> > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > +             raw_spin_unlock(&priv->lock);
> > > >       }
> > > >  }
> > > >
> > > > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops
> > > > = {  static const struct irq_chip irqc_chip = {
> > > >       .name                   = "rzg2l-irqc",
> > > >       .irq_eoi                = rzg2l_irqc_eoi,
> > > > -     .irq_mask               = irq_chip_mask_parent,
> > > > -     .irq_unmask             = irq_chip_unmask_parent,
> > > > +     .irq_mask               = rzg2l_irqc_mask,
> > > > +     .irq_unmask             = rzg2l_irqc_unmask,
> > >
> > > I feel this will be clean, if we have
> > >
> > > static const struct irq_chip rzg2l_irqc_chip = {
> > >         .name                   = "rzg2l-irqc",
> > >         ...
> > >         .irq_mask               = irq_chip_mask_parent,
> > >         .irq_unmask             = irq_chip_unmask_parent,
> > >         ....
> > > };
> > >
> > > static const struct irq_chip rzfive_irqc_chip = {
> > >         .name                   = "rzfive-irqc",
> > >         ...
> > >         .irq_mask               = rzfive_irqc_mask,
> > >         .irq_unmask             = rzfive_irqc_unmask,
> > >         ....
> > > };
> > >
> > > And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see
> > > below
> > >
> > > return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip); return
> > > rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
> > >
> > If we do the above we are stuck with "struct irq_chip" as data, for further upcoming SoCs (for
> > example RZ/V2H) which have more features we need to pass custom data to handle these features.
>
> That time device data can be extended like below
>
> struct rz_g2l_irq_chip {
>         struct irq_chip;
>         void *data; /* custom data */
> }
>
Ok, but i'll wait for Geert to come back on this as Geert suggested to
me to do it this way.

Cheers,
Prabhakar

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, Apr 4, 2024 at 3:35 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Apr 4, 2024 at 2:31 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > > On Thu, Apr 4, 2024 at 8:44 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > -----Original Message-----
> > > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as
> > > > > compared to the RZ/G2L (family) SoC.
> > > > >
> > > > > Introduce masking/unmasking support for IRQ and TINT interrupts in
> > > > > IRQC controller driver. Two new registers, IMSK and TMSK, are
> > > > > defined to handle masking on RZ/Five SoC. The implementation
> > > > > utilizes a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a
> > > specific controller instance.
> > > > >
> > > > > Signed-off-by: Lad Prabhakar
> > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > ---
> > > > > v1->v2
> > > > > - Added IRQCHIP_MATCH() for RZ/Five
> > > > > - Retaining a copy of OF data in priv
> > > > > - Rebased the changes
> > > > > ---
> > > > >  drivers/irqchip/irq-renesas-rzg2l.c | 137
> > > > > +++++++++++++++++++++++++++-
> > > > >  1 file changed, 132 insertions(+), 5 deletions(-)
> > > > >
> > > > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > index f6484bf15e0b..6fa8d65605dc 100644
> > > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > @@ -37,6 +37,8 @@
> > > > >  #define TSSEL_SHIFT(n)                       (8 * (n))
> > > > >  #define TSSEL_MASK                   GENMASK(7, 0)
> > > > >  #define IRQ_MASK                     0x3
> > > > > +#define IMSK                         0x10010
> > > > > +#define TMSK                         0x10020
> > > > >
> > > > >  #define TSSR_OFFSET(n)                       ((n) % 4)
> > > > >  #define TSSR_INDEX(n)                        ((n) / 4)
> > > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > > > >       u32     titsr[2];
> > > > >  };
> > > > >
> > > > > +/**
> > > > > + * struct rzg2l_irqc_of_data - OF data structure
> > > > > + * @mask_supported: Indicates if mask registers are available  */
> > > > > +struct rzg2l_irqc_of_data {
> > > > > +     bool    mask_supported;
> > > > > +};
> > > > > +
> > > > >  /**
> > > > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > > > >   * @base:    Controller's base address
> > > > > + * @data:    OF data pointer
> > > > >   * @fwspec:  IRQ firmware specific data
> > > > >   * @lock:    Lock to serialize access to hardware registers
> > > > >   * @cache:   Registers cache for suspend/resume
> > > > >   */
> > > > >  static struct rzg2l_irqc_priv {
> > > > >       void __iomem                    *base;
> > > > > +     const struct rzg2l_irqc_of_data *data;
> > > > >       struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> > > > >       raw_spinlock_t                  lock;
> > > > >       struct rzg2l_irqc_reg_cache     cache;
> > > > > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> > > > >       irq_chip_eoi_parent(d);
> > > > >  }
> > > > >
> > > > > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > +                                       unsigned int hwirq) {
> > > > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > > > +
> > > > > +     writel_relaxed(imsk | bit, priv->base + IMSK); }
> > > > > +
> > > > > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > +                                         unsigned int hwirq) {
> > > > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > > > +
> > > > > +     writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > > > > +
> > > > > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > +                                        unsigned int hwirq) {
> > > > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > > > +
> > > > > +     writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > > > > +
> > > > > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > +                                          unsigned int hwirq) {
> > > > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > > > +
> > > > > +     writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > > > > +
> > > > > +/* Must be called while priv->lock is held */ static void
> > > > > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > > > +hwirq) {
> > > > > +     if (!priv->data->mask_supported)
> > > > > +             return;
> > > > > +
> > > > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > > > +             rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > > > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > > > +             rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > > > > +
> > > > > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > > +
> > > > > +     raw_spin_lock(&priv->lock);
> > > > > +     rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > > > > +     raw_spin_unlock(&priv->lock);
> > > > > +     irq_chip_mask_parent(d);
> > > > > +}
> > > > > +
> > > > > +/* Must be called while priv->lock is held */ static void
> > > > > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > > > +hwirq) {
> > > > > +     if (!priv->data->mask_supported)
> > > > > +             return;
> > > > > +
> > > > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > > > +             rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > > > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > > > +             rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > > > > +
> > > > > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > > +
> > > > > +     raw_spin_lock(&priv->lock);
> > > > > +     rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > > > > +     raw_spin_unlock(&priv->lock);
> > > > > +     irq_chip_unmask_parent(d);
> > > > > +}
> > > > > +
> > > > >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool
> > > > > enable)  {
> > > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > >       unsigned int hw_irq = irqd_to_hwirq(d);
> > > > >
> > > > >       if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > > > > -             struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > >               u32 offset = hw_irq - IRQC_TINT_START;
> > > > >               u32 tssr_offset = TSSR_OFFSET(offset);
> > > > >               u8 tssr_index = TSSR_INDEX(offset);
> > > > >               u32 reg;
> > > > >
> > > > >               raw_spin_lock(&priv->lock);
> > > > > +             if (enable)
> > > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > > +             else
> > > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > >               reg = readl_relaxed(priv->base + TSSR(tssr_index));
> > > > >               if (enable)
> > > > >                       reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@
> > > > > -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> > > > >                       reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> > > > >               writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > > > >               raw_spin_unlock(&priv->lock);
> > > > > +     } else {
> > > > > +             raw_spin_lock(&priv->lock);
> > > > > +             if (enable)
> > > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > > +             else
> > > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > > +             raw_spin_unlock(&priv->lock);
> > > > >       }
> > > > >  }
> > > > >
> > > > > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops
> > > > > = {  static const struct irq_chip irqc_chip = {
> > > > >       .name                   = "rzg2l-irqc",
> > > > >       .irq_eoi                = rzg2l_irqc_eoi,
> > > > > -     .irq_mask               = irq_chip_mask_parent,
> > > > > -     .irq_unmask             = irq_chip_unmask_parent,
> > > > > +     .irq_mask               = rzg2l_irqc_mask,
> > > > > +     .irq_unmask             = rzg2l_irqc_unmask,
> > > >
> > > > I feel this will be clean, if we have
> > > >
> > > > static const struct irq_chip rzg2l_irqc_chip = {
> > > >         .name                   = "rzg2l-irqc",
> > > >         ...
> > > >         .irq_mask               = irq_chip_mask_parent,
> > > >         .irq_unmask             = irq_chip_unmask_parent,
> > > >         ....
> > > > };
> > > >
> > > > static const struct irq_chip rzfive_irqc_chip = {
> > > >         .name                   = "rzfive-irqc",
> > > >         ...
> > > >         .irq_mask               = rzfive_irqc_mask,
> > > >         .irq_unmask             = rzfive_irqc_unmask,
> > > >         ....
> > > > };
> > > >
> > > > And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see
> > > > below
> > > >
> > > > return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip); return
> > > > rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
> > > >
> > > If we do the above we are stuck with "struct irq_chip" as data, for further upcoming SoCs (for
> > > example RZ/V2H) which have more features we need to pass custom data to handle these features.
> >
> > That time device data can be extended like below
> >
> > struct rz_g2l_irq_chip {
> >         struct irq_chip;
> >         void *data; /* custom data */
> > }
> >
> Ok, but i'll wait for Geert to come back on this as Geert suggested to
> me to do it this way.

I agree with Biju.

Having separate irq_chips lets us avoid taking the spinlock on RZ/G2L.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Lad, Prabhakar]

Hi Geert,

On Thu, Apr 18, 2024 at 4:13 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Thu, Apr 4, 2024 at 3:35 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Thu, Apr 4, 2024 at 2:31 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > -----Original Message-----
> > > > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > > > On Thu, Apr 4, 2024 at 8:44 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > > -----Original Message-----
> > > > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as
> > > > > > compared to the RZ/G2L (family) SoC.
> > > > > >
> > > > > > Introduce masking/unmasking support for IRQ and TINT interrupts in
> > > > > > IRQC controller driver. Two new registers, IMSK and TMSK, are
> > > > > > defined to handle masking on RZ/Five SoC. The implementation
> > > > > > utilizes a new data structure, `struct rzg2l_irqc_data`, to determine mask support for a
> > > > specific controller instance.
> > > > > >
> > > > > > Signed-off-by: Lad Prabhakar
> > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > ---
> > > > > > v1->v2
> > > > > > - Added IRQCHIP_MATCH() for RZ/Five
> > > > > > - Retaining a copy of OF data in priv
> > > > > > - Rebased the changes
> > > > > > ---
> > > > > >  drivers/irqchip/irq-renesas-rzg2l.c | 137
> > > > > > +++++++++++++++++++++++++++-
> > > > > >  1 file changed, 132 insertions(+), 5 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > index f6484bf15e0b..6fa8d65605dc 100644
> > > > > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > > > > @@ -37,6 +37,8 @@
> > > > > >  #define TSSEL_SHIFT(n)                       (8 * (n))
> > > > > >  #define TSSEL_MASK                   GENMASK(7, 0)
> > > > > >  #define IRQ_MASK                     0x3
> > > > > > +#define IMSK                         0x10010
> > > > > > +#define TMSK                         0x10020
> > > > > >
> > > > > >  #define TSSR_OFFSET(n)                       ((n) % 4)
> > > > > >  #define TSSR_INDEX(n)                        ((n) / 4)
> > > > > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > > > > >       u32     titsr[2];
> > > > > >  };
> > > > > >
> > > > > > +/**
> > > > > > + * struct rzg2l_irqc_of_data - OF data structure
> > > > > > + * @mask_supported: Indicates if mask registers are available  */
> > > > > > +struct rzg2l_irqc_of_data {
> > > > > > +     bool    mask_supported;
> > > > > > +};
> > > > > > +
> > > > > >  /**
> > > > > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > > > > >   * @base:    Controller's base address
> > > > > > + * @data:    OF data pointer
> > > > > >   * @fwspec:  IRQ firmware specific data
> > > > > >   * @lock:    Lock to serialize access to hardware registers
> > > > > >   * @cache:   Registers cache for suspend/resume
> > > > > >   */
> > > > > >  static struct rzg2l_irqc_priv {
> > > > > >       void __iomem                    *base;
> > > > > > +     const struct rzg2l_irqc_of_data *data;
> > > > > >       struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> > > > > >       raw_spinlock_t                  lock;
> > > > > >       struct rzg2l_irqc_reg_cache     cache;
> > > > > > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> > > > > >       irq_chip_eoi_parent(d);
> > > > > >  }
> > > > > >
> > > > > > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > > +                                       unsigned int hwirq) {
> > > > > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > > > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > > > > +
> > > > > > +     writel_relaxed(imsk | bit, priv->base + IMSK); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > > +                                         unsigned int hwirq) {
> > > > > > +     u32 imsk = readl_relaxed(priv->base + IMSK);
> > > > > > +     u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > > > > > +
> > > > > > +     writel_relaxed(imsk & ~bit, priv->base + IMSK); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > > +                                        unsigned int hwirq) {
> > > > > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > > > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > > > > +
> > > > > > +     writel_relaxed(tmsk | bit, priv->base + TMSK); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > > > > > +                                          unsigned int hwirq) {
> > > > > > +     u32 tmsk = readl_relaxed(priv->base + TMSK);
> > > > > > +     u32 bit = BIT(hwirq - IRQC_TINT_START);
> > > > > > +
> > > > > > +     writel_relaxed(tmsk & ~bit, priv->base + TMSK); }
> > > > > > +
> > > > > > +/* Must be called while priv->lock is held */ static void
> > > > > > +rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > > > > +hwirq) {
> > > > > > +     if (!priv->data->mask_supported)
> > > > > > +             return;
> > > > > > +
> > > > > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > > > > +             rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > > > > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > > > > +             rzg2l_irqc_mask_tint_interrupt(priv, hwirq); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_mask(struct irq_data *d) {
> > > > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > > > +
> > > > > > +     raw_spin_lock(&priv->lock);
> > > > > > +     rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > > > > > +     raw_spin_unlock(&priv->lock);
> > > > > > +     irq_chip_mask_parent(d);
> > > > > > +}
> > > > > > +
> > > > > > +/* Must be called while priv->lock is held */ static void
> > > > > > +rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int
> > > > > > +hwirq) {
> > > > > > +     if (!priv->data->mask_supported)
> > > > > > +             return;
> > > > > > +
> > > > > > +     if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > > > > > +             rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > > > > > +     else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > > > > > +             rzg2l_irqc_unmask_tint_interrupt(priv, hwirq); }
> > > > > > +
> > > > > > +static void rzg2l_irqc_unmask(struct irq_data *d) {
> > > > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > > > +
> > > > > > +     raw_spin_lock(&priv->lock);
> > > > > > +     rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > > > > > +     raw_spin_unlock(&priv->lock);
> > > > > > +     irq_chip_unmask_parent(d);
> > > > > > +}
> > > > > > +
> > > > > >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool
> > > > > > enable)  {
> > > > > > +     struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > > >       unsigned int hw_irq = irqd_to_hwirq(d);
> > > > > >
> > > > > >       if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > > > > > -             struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > > > > >               u32 offset = hw_irq - IRQC_TINT_START;
> > > > > >               u32 tssr_offset = TSSR_OFFSET(offset);
> > > > > >               u8 tssr_index = TSSR_INDEX(offset);
> > > > > >               u32 reg;
> > > > > >
> > > > > >               raw_spin_lock(&priv->lock);
> > > > > > +             if (enable)
> > > > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > > > +             else
> > > > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > > >               reg = readl_relaxed(priv->base + TSSR(tssr_index));
> > > > > >               if (enable)
> > > > > >                       reg |= TIEN << TSSEL_SHIFT(tssr_offset); @@
> > > > > > -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> > > > > >                       reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> > > > > >               writel_relaxed(reg, priv->base + TSSR(tssr_index));
> > > > > >               raw_spin_unlock(&priv->lock);
> > > > > > +     } else {
> > > > > > +             raw_spin_lock(&priv->lock);
> > > > > > +             if (enable)
> > > > > > +                     rzg2l_irqc_unmask_once(priv, hw_irq);
> > > > > > +             else
> > > > > > +                     rzg2l_irqc_mask_once(priv, hw_irq);
> > > > > > +             raw_spin_unlock(&priv->lock);
> > > > > >       }
> > > > > >  }
> > > > > >
> > > > > > @@ -324,8 +427,8 @@ static struct syscore_ops rzg2l_irqc_syscore_ops
> > > > > > = {  static const struct irq_chip irqc_chip = {
> > > > > >       .name                   = "rzg2l-irqc",
> > > > > >       .irq_eoi                = rzg2l_irqc_eoi,
> > > > > > -     .irq_mask               = irq_chip_mask_parent,
> > > > > > -     .irq_unmask             = irq_chip_unmask_parent,
> > > > > > +     .irq_mask               = rzg2l_irqc_mask,
> > > > > > +     .irq_unmask             = rzg2l_irqc_unmask,
> > > > >
> > > > > I feel this will be clean, if we have
> > > > >
> > > > > static const struct irq_chip rzg2l_irqc_chip = {
> > > > >         .name                   = "rzg2l-irqc",
> > > > >         ...
> > > > >         .irq_mask               = irq_chip_mask_parent,
> > > > >         .irq_unmask             = irq_chip_unmask_parent,
> > > > >         ....
> > > > > };
> > > > >
> > > > > static const struct irq_chip rzfive_irqc_chip = {
> > > > >         .name                   = "rzfive-irqc",
> > > > >         ...
> > > > >         .irq_mask               = rzfive_irqc_mask,
> > > > >         .irq_unmask             = rzfive_irqc_unmask,
> > > > >         ....
> > > > > };
> > > > >
> > > > > And passing this in rzg2l_irqc_init() and rzfive_irqc_init(), see
> > > > > below
> > > > >
> > > > > return rzg2l_irqc_init_helper(node, parent, & rzg2l_irqc_chip); return
> > > > > rzg2l_irqc_init_helper(node, parent, & rzfive_irqc_chip);
> > > > >
> > > > If we do the above we are stuck with "struct irq_chip" as data, for further upcoming SoCs (for
> > > > example RZ/V2H) which have more features we need to pass custom data to handle these features.
> > >
> > > That time device data can be extended like below
> > >
> > > struct rz_g2l_irq_chip {
> > >         struct irq_chip;
> > >         void *data; /* custom data */
> > > }
> > >
> > Ok, but i'll wait for Geert to come back on this as Geert suggested to
> > me to do it this way.
>
> I agree with Biju.
>
> Having separate irq_chips lets us avoid taking the spinlock on RZ/G2L.
>
Agreed, I will add separate irq_chips.

Cheers,
Prabhakar

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, Apr 3, 2024 at 10:36 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared
> to the RZ/G2L (family) SoC.
>
> Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC
> controller driver. Two new registers, IMSK and TMSK, are defined to
> handle masking on RZ/Five SoC. The implementation utilizes a new data
> structure, `struct rzg2l_irqc_data`, to determine mask support for a
> specific controller instance.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - Added IRQCHIP_MATCH() for RZ/Five
> - Retaining a copy of OF data in priv
> - Rebased the changes

Thanks for the update!

> --- a/drivers/irqchip/irq-renesas-rzg2l.c
> +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> @@ -37,6 +37,8 @@
>  #define TSSEL_SHIFT(n)                 (8 * (n))
>  #define TSSEL_MASK                     GENMASK(7, 0)
>  #define IRQ_MASK                       0x3
> +#define IMSK                           0x10010
> +#define TMSK                           0x10020
>
>  #define TSSR_OFFSET(n)                 ((n) % 4)
>  #define TSSR_INDEX(n)                  ((n) / 4)
> @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
>         u32     titsr[2];
>  };
>
> +/**
> + * struct rzg2l_irqc_of_data - OF data structure
> + * @mask_supported: Indicates if mask registers are available
> + */
> +struct rzg2l_irqc_of_data {
> +       bool    mask_supported;
> +};
> +
>  /**
>   * struct rzg2l_irqc_priv - IRQ controller private data structure
>   * @base:      Controller's base address
> + * @data:      OF data pointer
>   * @fwspec:    IRQ firmware specific data
>   * @lock:      Lock to serialize access to hardware registers
>   * @cache:     Registers cache for suspend/resume
>   */
>  static struct rzg2l_irqc_priv {
>         void __iomem                    *base;
> +       const struct rzg2l_irqc_of_data *data;

That's not a copy, but a pointer.

>         struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
>         raw_spinlock_t                  lock;
>         struct rzg2l_irqc_reg_cache     cache;
> @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
>         irq_chip_eoi_parent(d);
>  }
>
> +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> +                                         unsigned int hwirq)
> +{
> +       u32 imsk = readl_relaxed(priv->base + IMSK);
> +       u32 bit = BIT(hwirq - IRQC_IRQ_START);
> +
> +       writel_relaxed(imsk | bit, priv->base + IMSK);
> +}
> +
> +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> +                                           unsigned int hwirq)
> +{
> +       u32 imsk = readl_relaxed(priv->base + IMSK);
> +       u32 bit = BIT(hwirq - IRQC_IRQ_START);
> +
> +       writel_relaxed(imsk & ~bit, priv->base + IMSK);
> +}
> +
> +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> +                                          unsigned int hwirq)
> +{
> +       u32 tmsk = readl_relaxed(priv->base + TMSK);
> +       u32 bit = BIT(hwirq - IRQC_TINT_START);
> +
> +       writel_relaxed(tmsk | bit, priv->base + TMSK);
> +}
> +
> +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> +                                            unsigned int hwirq)
> +{
> +       u32 tmsk = readl_relaxed(priv->base + TMSK);
> +       u32 bit = BIT(hwirq - IRQC_TINT_START);
> +
> +       writel_relaxed(tmsk & ~bit, priv->base + TMSK);
> +}
> +
> +/* Must be called while priv->lock is held */
> +static void rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> +{
> +       if (!priv->data->mask_supported)
> +               return;
> +
> +       if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> +               rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> +       else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> +               rzg2l_irqc_mask_tint_interrupt(priv, hwirq);
> +}
> +
> +static void rzg2l_irqc_mask(struct irq_data *d)
> +{
> +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> +
> +       raw_spin_lock(&priv->lock);
> +       rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> +       raw_spin_unlock(&priv->lock);
> +       irq_chip_mask_parent(d);
> +}
> +
> +/* Must be called while priv->lock is held */
> +static void rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> +{
> +       if (!priv->data->mask_supported)
> +               return;
> +
> +       if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> +               rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> +       else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> +               rzg2l_irqc_unmask_tint_interrupt(priv, hwirq);
> +}
> +
> +static void rzg2l_irqc_unmask(struct irq_data *d)
> +{
> +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> +
> +       raw_spin_lock(&priv->lock);
> +       rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> +       raw_spin_unlock(&priv->lock);
> +       irq_chip_unmask_parent(d);
> +}
> +
>  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
>  {
> +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
>         unsigned int hw_irq = irqd_to_hwirq(d);
>
>         if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> -               struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
>                 u32 offset = hw_irq - IRQC_TINT_START;
>                 u32 tssr_offset = TSSR_OFFSET(offset);
>                 u8 tssr_index = TSSR_INDEX(offset);
>                 u32 reg;
>
>                 raw_spin_lock(&priv->lock);
> +               if (enable)
> +                       rzg2l_irqc_unmask_once(priv, hw_irq);
> +               else
> +                       rzg2l_irqc_mask_once(priv, hw_irq);

You already know this is a TINT interrupt, so you could call
rzg2l_irqc_(un)mask_irq_interrupt() directly.

>                 reg = readl_relaxed(priv->base + TSSR(tssr_index));
>                 if (enable)
>                         reg |= TIEN << TSSEL_SHIFT(tssr_offset);
> @@ -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
>                         reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
>                 writel_relaxed(reg, priv->base + TSSR(tssr_index));
>                 raw_spin_unlock(&priv->lock);
> +       } else {
> +               raw_spin_lock(&priv->lock);
> +               if (enable)
> +                       rzg2l_irqc_unmask_once(priv, hw_irq);
> +               else
> +                       rzg2l_irqc_mask_once(priv, hw_irq);

Likewise.

> +               raw_spin_unlock(&priv->lock);
>         }
>  }

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Thu, Apr 18, 2024 at 4:11 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, Apr 3, 2024 at 10:36 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared
> > to the RZ/G2L (family) SoC.
> >
> > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC
> > controller driver. Two new registers, IMSK and TMSK, are defined to
> > handle masking on RZ/Five SoC. The implementation utilizes a new data
> > structure, `struct rzg2l_irqc_data`, to determine mask support for a
> > specific controller instance.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - Added IRQCHIP_MATCH() for RZ/Five
> > - Retaining a copy of OF data in priv
> > - Rebased the changes
>
> Thanks for the update!
>
> > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > @@ -37,6 +37,8 @@
> >  #define TSSEL_SHIFT(n)                 (8 * (n))
> >  #define TSSEL_MASK                     GENMASK(7, 0)
> >  #define IRQ_MASK                       0x3
> > +#define IMSK                           0x10010
> > +#define TMSK                           0x10020
> >
> >  #define TSSR_OFFSET(n)                 ((n) % 4)
> >  #define TSSR_INDEX(n)                  ((n) / 4)
> > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> >         u32     titsr[2];
> >  };
> >
> > +/**
> > + * struct rzg2l_irqc_of_data - OF data structure
> > + * @mask_supported: Indicates if mask registers are available
> > + */
> > +struct rzg2l_irqc_of_data {
> > +       bool    mask_supported;
> > +};
> > +
> >  /**
> >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> >   * @base:      Controller's base address
> > + * @data:      OF data pointer
> >   * @fwspec:    IRQ firmware specific data
> >   * @lock:      Lock to serialize access to hardware registers
> >   * @cache:     Registers cache for suspend/resume
> >   */
> >  static struct rzg2l_irqc_priv {
> >         void __iomem                    *base;
> > +       const struct rzg2l_irqc_of_data *data;
>
> That's not a copy, but a pointer.
>
Oops, should that be OK or shall I create a copy instead?

> >         struct irq_fwspec               fwspec[IRQC_NUM_IRQ];
> >         raw_spinlock_t                  lock;
> >         struct rzg2l_irqc_reg_cache     cache;
> > @@ -138,18 +150,102 @@ static void rzg2l_irqc_eoi(struct irq_data *d)
> >         irq_chip_eoi_parent(d);
> >  }
> >
> > +static void rzg2l_irqc_mask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                         unsigned int hwirq)
> > +{
> > +       u32 imsk = readl_relaxed(priv->base + IMSK);
> > +       u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > +       writel_relaxed(imsk | bit, priv->base + IMSK);
> > +}
> > +
> > +static void rzg2l_irqc_unmask_irq_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                           unsigned int hwirq)
> > +{
> > +       u32 imsk = readl_relaxed(priv->base + IMSK);
> > +       u32 bit = BIT(hwirq - IRQC_IRQ_START);
> > +
> > +       writel_relaxed(imsk & ~bit, priv->base + IMSK);
> > +}
> > +
> > +static void rzg2l_irqc_mask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                          unsigned int hwirq)
> > +{
> > +       u32 tmsk = readl_relaxed(priv->base + TMSK);
> > +       u32 bit = BIT(hwirq - IRQC_TINT_START);
> > +
> > +       writel_relaxed(tmsk | bit, priv->base + TMSK);
> > +}
> > +
> > +static void rzg2l_irqc_unmask_tint_interrupt(struct rzg2l_irqc_priv *priv,
> > +                                            unsigned int hwirq)
> > +{
> > +       u32 tmsk = readl_relaxed(priv->base + TMSK);
> > +       u32 bit = BIT(hwirq - IRQC_TINT_START);
> > +
> > +       writel_relaxed(tmsk & ~bit, priv->base + TMSK);
> > +}
> > +
> > +/* Must be called while priv->lock is held */
> > +static void rzg2l_irqc_mask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> > +{
> > +       if (!priv->data->mask_supported)
> > +               return;
> > +
> > +       if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > +               rzg2l_irqc_mask_irq_interrupt(priv, hwirq);
> > +       else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > +               rzg2l_irqc_mask_tint_interrupt(priv, hwirq);
> > +}
> > +
> > +static void rzg2l_irqc_mask(struct irq_data *d)
> > +{
> > +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > +
> > +       raw_spin_lock(&priv->lock);
> > +       rzg2l_irqc_mask_once(priv, irqd_to_hwirq(d));
> > +       raw_spin_unlock(&priv->lock);
> > +       irq_chip_mask_parent(d);
> > +}
> > +
> > +/* Must be called while priv->lock is held */
> > +static void rzg2l_irqc_unmask_once(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
> > +{
> > +       if (!priv->data->mask_supported)
> > +               return;
> > +
> > +       if (hwirq >= IRQC_IRQ_START && hwirq <= IRQC_IRQ_COUNT)
> > +               rzg2l_irqc_unmask_irq_interrupt(priv, hwirq);
> > +       else if (hwirq >= IRQC_TINT_START && hwirq < IRQC_NUM_IRQ)
> > +               rzg2l_irqc_unmask_tint_interrupt(priv, hwirq);
> > +}
> > +
> > +static void rzg2l_irqc_unmask(struct irq_data *d)
> > +{
> > +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> > +
> > +       raw_spin_lock(&priv->lock);
> > +       rzg2l_irqc_unmask_once(priv, irqd_to_hwirq(d));
> > +       raw_spin_unlock(&priv->lock);
> > +       irq_chip_unmask_parent(d);
> > +}
> > +
> >  static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> >  {
> > +       struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> >         unsigned int hw_irq = irqd_to_hwirq(d);
> >
> >         if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
> > -               struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
> >                 u32 offset = hw_irq - IRQC_TINT_START;
> >                 u32 tssr_offset = TSSR_OFFSET(offset);
> >                 u8 tssr_index = TSSR_INDEX(offset);
> >                 u32 reg;
> >
> >                 raw_spin_lock(&priv->lock);
> > +               if (enable)
> > +                       rzg2l_irqc_unmask_once(priv, hw_irq);
> > +               else
> > +                       rzg2l_irqc_mask_once(priv, hw_irq);
>
> You already know this is a TINT interrupt, so you could call
> rzg2l_irqc_(un)mask_irq_interrupt() directly.
>
Agreed.

> >                 reg = readl_relaxed(priv->base + TSSR(tssr_index));
> >                 if (enable)
> >                         reg |= TIEN << TSSEL_SHIFT(tssr_offset);
> > @@ -157,6 +253,13 @@ static void rzg2l_tint_irq_endisable(struct irq_data *d, bool enable)
> >                         reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
> >                 writel_relaxed(reg, priv->base + TSSR(tssr_index));
> >                 raw_spin_unlock(&priv->lock);
> > +       } else {
> > +               raw_spin_lock(&priv->lock);
> > +               if (enable)
> > +                       rzg2l_irqc_unmask_once(priv, hw_irq);
> > +               else
> > +                       rzg2l_irqc_mask_once(priv, hw_irq);
>
> Likewise.
>
OK.

Cheers,
Prabhakar

Re: [PATCH v2 2/5] irqchip/renesas-rzg2l: Add support for RZ/Five SoC

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, Apr 19, 2024 at 9:15 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, Apr 18, 2024 at 4:11 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Apr 3, 2024 at 10:36 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > The IX45 block has additional mask registers (NMSK/IMSK/TMSK) as compared
> > > to the RZ/G2L (family) SoC.
> > >
> > > Introduce masking/unmasking support for IRQ and TINT interrupts in IRQC
> > > controller driver. Two new registers, IMSK and TMSK, are defined to
> > > handle masking on RZ/Five SoC. The implementation utilizes a new data
> > > structure, `struct rzg2l_irqc_data`, to determine mask support for a
> > > specific controller instance.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - Added IRQCHIP_MATCH() for RZ/Five
> > > - Retaining a copy of OF data in priv
> > > - Rebased the changes
> >
> > Thanks for the update!
> >
> > > --- a/drivers/irqchip/irq-renesas-rzg2l.c
> > > +++ b/drivers/irqchip/irq-renesas-rzg2l.c
> > > @@ -66,15 +68,25 @@ struct rzg2l_irqc_reg_cache {
> > >         u32     titsr[2];
> > >  };
> > >
> > > +/**
> > > + * struct rzg2l_irqc_of_data - OF data structure
> > > + * @mask_supported: Indicates if mask registers are available
> > > + */
> > > +struct rzg2l_irqc_of_data {
> > > +       bool    mask_supported;
> > > +};
> > > +
> > >  /**
> > >   * struct rzg2l_irqc_priv - IRQ controller private data structure
> > >   * @base:      Controller's base address
> > > + * @data:      OF data pointer
> > >   * @fwspec:    IRQ firmware specific data
> > >   * @lock:      Lock to serialize access to hardware registers
> > >   * @cache:     Registers cache for suspend/resume
> > >   */
> > >  static struct rzg2l_irqc_priv {
> > >         void __iomem                    *base;
> > > +       const struct rzg2l_irqc_of_data *data;
> >
> > That's not a copy, but a pointer.
> >
> Oops, should that be OK or shall I create a copy instead?

If you would use a copy, all SoC-specific rzg2l_irqc_of_data structures
could become __initconst.

However, depending on how far you want to go with the irq_chip
separation, you may no longer need this field anyway.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 3/5] riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the IRQC node to RZ/Five (R9A07G043F) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- Dropped using SOC_PERIPHERAL_IRQ() macro
---
 arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 75 +++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
index f35324b9173c..e0ddf8f602c7 100644
--- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
@@ -54,6 +54,81 @@ &soc {
 	dma-noncoherent;
 	interrupt-parent = <&plic>;
 
+	irqc: interrupt-controller@110a0000 {
+		compatible = "renesas,r9a07g043f-irqc";
+		reg = <0 0x110a0000 0 0x20000>;
+		#interrupt-cells = <2>;
+		#address-cells = <0>;
+		interrupt-controller;
+		interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
+			     <33 IRQ_TYPE_LEVEL_HIGH>,
+			     <34 IRQ_TYPE_LEVEL_HIGH>,
+			     <35 IRQ_TYPE_LEVEL_HIGH>,
+			     <36 IRQ_TYPE_LEVEL_HIGH>,
+			     <37 IRQ_TYPE_LEVEL_HIGH>,
+			     <38 IRQ_TYPE_LEVEL_HIGH>,
+			     <39 IRQ_TYPE_LEVEL_HIGH>,
+			     <40 IRQ_TYPE_LEVEL_HIGH>,
+			     <476 IRQ_TYPE_LEVEL_HIGH>,
+			     <477 IRQ_TYPE_LEVEL_HIGH>,
+			     <478 IRQ_TYPE_LEVEL_HIGH>,
+			     <479 IRQ_TYPE_LEVEL_HIGH>,
+			     <480 IRQ_TYPE_LEVEL_HIGH>,
+			     <481 IRQ_TYPE_LEVEL_HIGH>,
+			     <482 IRQ_TYPE_LEVEL_HIGH>,
+			     <483 IRQ_TYPE_LEVEL_HIGH>,
+			     <484 IRQ_TYPE_LEVEL_HIGH>,
+			     <485 IRQ_TYPE_LEVEL_HIGH>,
+			     <486 IRQ_TYPE_LEVEL_HIGH>,
+			     <487 IRQ_TYPE_LEVEL_HIGH>,
+			     <488 IRQ_TYPE_LEVEL_HIGH>,
+			     <489 IRQ_TYPE_LEVEL_HIGH>,
+			     <490 IRQ_TYPE_LEVEL_HIGH>,
+			     <491 IRQ_TYPE_LEVEL_HIGH>,
+			     <492 IRQ_TYPE_LEVEL_HIGH>,
+			     <493 IRQ_TYPE_LEVEL_HIGH>,
+			     <494 IRQ_TYPE_LEVEL_HIGH>,
+			     <495 IRQ_TYPE_LEVEL_HIGH>,
+			     <496 IRQ_TYPE_LEVEL_HIGH>,
+			     <497 IRQ_TYPE_LEVEL_HIGH>,
+			     <498 IRQ_TYPE_LEVEL_HIGH>,
+			     <499 IRQ_TYPE_LEVEL_HIGH>,
+			     <500 IRQ_TYPE_LEVEL_HIGH>,
+			     <501 IRQ_TYPE_LEVEL_HIGH>,
+			     <502 IRQ_TYPE_LEVEL_HIGH>,
+			     <503 IRQ_TYPE_LEVEL_HIGH>,
+			     <504 IRQ_TYPE_LEVEL_HIGH>,
+			     <505 IRQ_TYPE_LEVEL_HIGH>,
+			     <506 IRQ_TYPE_LEVEL_HIGH>,
+			     <507 IRQ_TYPE_LEVEL_HIGH>,
+			     <57 IRQ_TYPE_LEVEL_HIGH>,
+			     <66 IRQ_TYPE_EDGE_RISING>,
+			     <67 IRQ_TYPE_EDGE_RISING>,
+			     <68 IRQ_TYPE_EDGE_RISING>,
+			     <69 IRQ_TYPE_EDGE_RISING>,
+			     <70 IRQ_TYPE_EDGE_RISING>,
+			     <71 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "nmi",
+				  "irq0", "irq1", "irq2", "irq3",
+				  "irq4", "irq5", "irq6", "irq7",
+				  "tint0", "tint1", "tint2", "tint3",
+				  "tint4", "tint5", "tint6", "tint7",
+				  "tint8", "tint9", "tint10", "tint11",
+				  "tint12", "tint13", "tint14", "tint15",
+				  "tint16", "tint17", "tint18", "tint19",
+				  "tint20", "tint21", "tint22", "tint23",
+				  "tint24", "tint25", "tint26", "tint27",
+				  "tint28", "tint29", "tint30", "tint31",
+				  "bus-err", "ec7tie1-0", "ec7tie2-0",
+				  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+				  "ec7tiovf-1";
+		clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>,
+			 <&cpg CPG_MOD R9A07G043_IAX45_PCLK>;
+		clock-names = "clk", "pclk";
+		power-domains = <&cpg>;
+		resets = <&cpg R9A07G043_IAX45_RESETN>;
+	};
+
 	plic: interrupt-controller@12c00000 {
 		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
 		#interrupt-cells = <2>;
-- 
2.34.1

Re: [PATCH v2 3/5] riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, Apr 3, 2024 at 10:36 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add the IRQC node to RZ/Five (R9A07G043F) SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for the update!

> ---
> v1->v2
> - Dropped using SOC_PERIPHERAL_IRQ() macro

and change the bus-err interrupt to from EDGE_RISING to LEVEL_HIGH,
to match the documentation ;-)

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.10, with patches 4/5 and 5/5.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v2 4/5] arm64: dts: renesas: r9a07g043: Move interrupt-parent property to common DTSI

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Now that we have added support for IRQC to both RZ/Five and RZ/G2UL SoCs
we can move the interrupt-parent for pinctrl node back to the common
shared r9a07g043.dtsi file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2
- Included RB tag from Geert
---
 arch/arm64/boot/dts/renesas/r9a07g043.dtsi  | 1 +
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ----
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 766c54b91acc..6212ee550f33 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -598,6 +598,7 @@ pinctrl: pinctrl@11030000 {
 			gpio-ranges = <&pinctrl 0 0 152>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
+			interrupt-parent = <&irqc>;
 			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
 			power-domains = <&cpg>;
 			resets = <&cpg R9A07G043_GPIO_RSTN>,
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 964b0a475eee..165bfcfef3bc 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -54,10 +54,6 @@ timer {
 	};
 };
 
-&pinctrl {
-	interrupt-parent = <&irqc>;
-};
-
 &soc {
 	interrupt-parent = <&gic>;
 
-- 
2.34.1

[PATCH v2 5/5] riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt properties from ETH0/1 nodes

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Now that we have enabled IRQC support for RZ/Five SoC switch to interrupt
mode for ethernet0/1 PHYs instead of polling mode.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v1->v2
- Included RB tag from Geert
---
 .../riscv/boot/dts/renesas/rzfive-smarc-som.dtsi | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
index 72d9b6fba526..86b2f15375ec 100644
--- a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -7,22 +7,6 @@
 
 #include <arm64/renesas/rzg2ul-smarc-som.dtsi>
 
-#if (!SW_ET0_EN_N)
-&eth0 {
-	phy0: ethernet-phy@7 {
-		/delete-property/ interrupt-parent;
-		/delete-property/ interrupts;
-	};
-};
-#endif
-
-&eth1 {
-	phy1: ethernet-phy@7 {
-		/delete-property/ interrupt-parent;
-		/delete-property/ interrupts;
-	};
-};
-
 &sbc {
 	status = "disabled";
 };
-- 
2.34.1