mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: John Madieu <john.madieu.xa@bp.renesas.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: "magnus.damm@gmail.com" <magnus.damm@gmail.com>,
	"robh@kernel.org" <robh@kernel.org>,
	"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
	"conor+dt@kernel.org" <conor+dt@kernel.org>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"sboyd@kernel.org" <sboyd@kernel.org>,
	"richardcochran@gmail.com" <richardcochran@gmail.com>,
	"linux-renesas-soc@vger.kernel.org"
	<linux-renesas-soc@vger.kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: RE: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
Date: Mon, 30 Jun 2025 16:53:50 +0000	[thread overview]
Message-ID: <OSCPR01MB14647BA02F34A7BA3C98D6CCFFF46A@OSCPR01MB14647.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <CAMuHMdU1mEfiL3e=NwSjTchpDXt1YTM3AkS7K3aR5h4FK94WCg@mail.gmail.com>

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Wednesday, June 25, 2025 5:13 PM
> To: John Madieu <john.madieu.xa@bp.renesas.com>
> Subject: Re: [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset
> signals for the GBETH IPs
> 
> Hi John,
> 
> On Mon, 23 Jun 2025 at 10:04, John Madieu <john.madieu.xa@bp.renesas.com>
> wrote:
> > Add clock and reset entries for the Gigabit Ethernet Interfaces (GBETH
> > 0-1) IPs found on the RZ/G3E SoC. This includes various PLLs,
> > dividers, and mux clocks needed by these two GBETH IPs.
> >
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
> > ---
> >
> > v2:
> > No changes but resending without dt-bindings patch
> >
> > v3:
> > Uses underscores instead of dashes in clock names
> 
> Thanks for the update!
> 
> > --- a/drivers/clk/renesas/r9a09g047-cpg.c
> > +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> 
> > +
> >  /* Mux clock tables */
> > +static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0",
> > +"et0_rxc_rx_clk" }; static const char * const smux2_gbe0_txclk[] = {
> > +".plleth_gbe0", "et0_txc_tx_clk" }; static const char * const
> > +smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxc_rx_clk" }; static
> > +const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1",
> > +"et1_txc_tx_clk" };
> 
> I have to ask you again: these still differ from the similar names used on
> RZ/V2H. Is there a reason for that? Will that cause issues later?
> Or is this to be sorted out only when the PHY driver will start supporting
> these clocks?
> 

I've discussed internally, and names must match. The next version will
then have appropriate names. Sorry for not mentioning it earlier.

> >  static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3",
> > ".pllcm33_div4" };  static const char * const smux2_xspi_clk1[] = {
> > ".smux2_xspi_clk0", ".pllcm33_div5" };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert

Regards,
John

> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds

  reply	other threads:[~2025-06-30 16:53 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-23  8:04 [PATCH v3 0/3] Add support for GBETH IPs found on RZ/G3E SoCs John Madieu
2025-06-23  8:04 ` [PATCH v3 1/3] clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs John Madieu
2025-06-25 15:12   ` Geert Uytterhoeven
2025-06-30 16:53     ` John Madieu [this message]
2025-06-23  8:04 ` [PATCH v3 2/3] arm64: dts: renesas: r9a09g047: Add GBETH nodes John Madieu
2025-06-26 12:31   ` Geert Uytterhoeven
2025-06-23  8:04 ` [PATCH v3 3/3] arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces John Madieu
2025-06-25 15:16   ` Geert Uytterhoeven
2025-06-26  7:51     ` Biju Das

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=OSCPR01MB14647BA02F34A7BA3C98D6CCFFF46A@OSCPR01MB14647.jpnprd01.prod.outlook.com \
    --to=john.madieu.xa@bp.renesas.com \
    --cc=biju.das.jz@bp.renesas.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=geert@linux-m68k.org \
    --cc=krzk+dt@kernel.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=magnus.damm@gmail.com \
    --cc=mturquette@baylibre.com \
    --cc=netdev@vger.kernel.org \
    --cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
    --cc=richardcochran@gmail.com \
    --cc=robh@kernel.org \
    --cc=sboyd@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®