RE: [PATCH v25 00/11] Add Renesas RZ/G3L SD/eMMC support

[Biju Das <biju.das.jz@bp.renesas.com>]

Hi Wolfram,

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: 11 November 2026 11:49
> Subject: Re: [PATCH v25 00/11] Add Renesas RZ/G3L SD/eMMC support
> 
> On Wed, Oct 28, 2026 at 12:51:17PM +0000, Biju Das wrote:
> > Hi All,
> >
> > The Renesas RZ/G3L SoC has:
> >
> > Channel 0 supports SD and eMMC (including HS400/HS400ES).
> > Channel 1 supports SD and eMMC (except for HS400).
> > Channel 2 supports SD.
> >
> > The SoC supports a maximum frequency of 150 MHz. The SD0 interface
> > does not support IOVS and PWEN in the SDHI register (no internal
> > regulator), unlike SD1 and SD2. It has an internal divider for all modes except HS400.
> > It also has a 2048-bit divider compared to 512 on others. Moreover
> > RZ/G3L supports HS400 enhanced strobe mode.
> >
> > This patch series support all modes except HS400. HS400 support will
> > be added later.
> >
> > This patch series tested on smarc-rz{v2l,g2l,g2lc,g2ul,g3s,g3l,g3e},
> > rz{v2h,t2h}-evk and hihope-rz{g2h,g2m,g2n} boards
> 
> Tested with a Renesas Salvator-XS board (R-Car M3N). I don't see bugs or performance regressions. I
> think the series is good to go!

Thanks for review and testing. The code is much better now
based on your review feedback.

Cheers,
Biju