[PATCH v3] arm64: dts: msm8916: Enable CoreSight STM component

[PATCH v3] arm64: dts: msm8916: Enable CoreSight STM component

[Leo Yan]

From: Georgi Djakov <georgi.djakov@linaro.org>

Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916,
which can benefit the CoreSight development on DB410c.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---

Changes from v2:
* Correct for author name.

Changes from v1:
* alphabetically and address ordering for DT node; pad addresses with
  zeroes (Stephan Gerhold).

 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi |  1 +
 arch/arm64/boot/dts/qcom/msm8916.dtsi     | 27 +++++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 3a9538e1ec97..2165b7415add 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -410,6 +410,7 @@ &wcd_codec {
 &funnel0 { status = "okay"; };
 &funnel1 { status = "okay"; };
 &replicator { status = "okay"; };
+&stm { status = "okay"; };
 &tpiu { status = "okay"; };
 
 &smd_rpm_regulators {
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 402e891a84ab..f02b976480d5 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -489,6 +489,26 @@ snoc: interconnect@580000 {
 				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
 		};
 
+		stm: stm@802000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0x00802000 0x1000>,
+			      <0x09280000 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+			clock-names = "apb_pclk", "atclk";
+
+			status = "disabled";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint = <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
 		/* System CTIs */
 		/* CTI 0 - TMC connections */
 		cti0: cti@810000 {
@@ -562,6 +582,13 @@ funnel0_in4: endpoint {
 						remote-endpoint = <&funnel1_out>;
 					};
 				};
+
+				port@7 {
+					reg = <7>;
+					funnel0_in7: endpoint {
+						remote-endpoint = <&stm_out>;
+					};
+				};
 			};
 
 			out-ports {
-- 
2.25.1

Re: [PATCH v3] arm64: dts: msm8916: Enable CoreSight STM component

[Stephan Gerhold]

On Sun, Mar 21, 2021 at 08:42:12PM +0800, Leo Yan wrote:
> From: Georgi Djakov <georgi.djakov@linaro.org>
> 
> Add DT binding for CoreSight System Trace Macrocell (STM) on msm8916,
> which can benefit the CoreSight development on DB410c.
> 
> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>

Thanks for sending the new patch so quickly!

The changes look good to me but I cannot really say if they are fully
correct or work correctly. (Actually I have no idea how to use coresight
or how it is useful! :D)

FWIW:
Acked-by: Stephan Gerhold <stephan@gerhold.net>

> ---
> 
> Changes from v2:
> * Correct for author name.
> 
> Changes from v1:
> * alphabetically and address ordering for DT node; pad addresses with
>   zeroes (Stephan Gerhold).
> 
>  arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi |  1 +
>  arch/arm64/boot/dts/qcom/msm8916.dtsi     | 27 +++++++++++++++++++++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> index 3a9538e1ec97..2165b7415add 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> @@ -410,6 +410,7 @@ &wcd_codec {
>  &funnel0 { status = "okay"; };
>  &funnel1 { status = "okay"; };
>  &replicator { status = "okay"; };
> +&stm { status = "okay"; };
>  &tpiu { status = "okay"; };
>  
>  &smd_rpm_regulators {
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index 402e891a84ab..f02b976480d5 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -489,6 +489,26 @@ snoc: interconnect@580000 {
>  				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
>  		};
>  
> +		stm: stm@802000 {
> +			compatible = "arm,coresight-stm", "arm,primecell";
> +			reg = <0x00802000 0x1000>,
> +			      <0x09280000 0x180000>;
> +			reg-names = "stm-base", "stm-stimulus-base";
> +
> +			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
> +			clock-names = "apb_pclk", "atclk";
> +
> +			status = "disabled";
> +
> +			out-ports {
> +				port {
> +					stm_out: endpoint {
> +						remote-endpoint = <&funnel0_in7>;
> +					};
> +				};
> +			};
> +		};
> +
>  		/* System CTIs */
>  		/* CTI 0 - TMC connections */
>  		cti0: cti@810000 {
> @@ -562,6 +582,13 @@ funnel0_in4: endpoint {
>  						remote-endpoint = <&funnel1_out>;
>  					};
>  				};
> +
> +				port@7 {
> +					reg = <7>;
> +					funnel0_in7: endpoint {
> +						remote-endpoint = <&stm_out>;
> +					};
> +				};
>  			};
>  
>  			out-ports {
> -- 
> 2.25.1
>