From: Andrew Lunn <andrew@lunn.ch>
To: Peter Geis <pgwipeout@gmail.com>
Cc: Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
"David S . Miller" <davem@davemloft.net>,
Jakub Kicinski <kuba@kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux Kernel Network Developers <netdev@vger.kernel.org>,
"open list:ARM/Rockchip SoC..."
<linux-rockchip@lists.infradead.org>
Subject: Re: [PATCH v3] net: phy: add driver for Motorcomm yt8511 phy
Date: Fri, 14 May 2021 16:52:26 +0200 [thread overview]
Message-ID: <YJ6OqpRTo+rlfb51@lunn.ch> (raw)
In-Reply-To: <CAMdYzYrSB0G7jfG9fo85X0DxVG_r-qaWUyVAa5paAW0ugLvoxw@mail.gmail.com>
> > I also wonder about bits 15:12 of PHY EXT ODH: Delay and driver
> > strength CFG register.
>
> The default value *works*, and from an emi perspective we want the
> lowest strength single that is reliable.
I was not meaning signal strength, but Txc_delay_sel_fe,
selecte tx_clk_rgmii delay in chip which is used to latch txd_rgmii
in 100BT/10BTe mode. 150ps step. Default value 15 means about 2ns
clock delay compared to txd_rgmii in typical cornor.
[Typos courtesy of the datasheet, not me!]
This sounds like more RGMII delays. It seems like PHY EXT 0CH is about
1G mode, and PHY EXT 0DH is about 10/100 mode. I think you probably
need to set this bits as well. Have you tested against a link peer at
10 Half? 100 Full?
Andrew
next prev parent reply other threads:[~2021-05-14 14:52 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-14 11:58 Peter Geis
2021-05-14 13:09 ` Heiner Kallweit
2021-05-14 14:04 ` Peter Geis
2021-05-14 13:09 ` Russell King (Oracle)
2021-05-14 14:09 ` Peter Geis
2021-05-14 13:24 ` Andrew Lunn
2021-05-14 14:14 ` Peter Geis
2021-05-14 14:52 ` Andrew Lunn [this message]
2021-05-14 15:25 ` Peter Geis
2021-05-14 15:41 ` Andrew Lunn
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