From: Borislav Petkov <bp@alien8.de>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Ser Olmy <ser.olmy@protonmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
x86@kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [regression] commit d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
Date: Thu, 14 Oct 2021 21:08:45 +0200 [thread overview]
Message-ID: <YWiAPQCRm4RnOiCd@zn.tnic> (raw)
In-Reply-To: <YWh7GgCgdtwRj3GU@intel.com>
On Thu, Oct 14, 2021 at 09:46:50PM +0300, Ville Syrjälä wrote:
> I figured you can write a reasonably succinct commit message, instead
> of having me ramble on incoherently. ATM I don't even know what mxcsr
> is or why clobbering it would cause floating point exceptions with
> sse specifically.
>
> But I can certainly ramble, if you prefer that.
Well, you can simply say that d298b03506d3 was supposed to mask out the
reserved bits in the MXCSR register but the author mistakenly used the
negation of the mask.
And if the commit message is not explaining stuff properly, I'll fix it
up, no worries there.
But your call - I'm done for today and I'll do a patch tomorrow. That
is, unless you haven't decided that you wish to write one in the
meantime and you've sent it to me overnight.
:-)))
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2021-10-14 19:08 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-14 11:44 Ville Syrjälä
2021-10-14 14:27 ` Borislav Petkov
2021-10-14 14:34 ` Ville Syrjälä
2021-10-14 14:43 ` Ville Syrjälä
2021-10-14 14:56 ` Borislav Petkov
2021-10-14 15:03 ` Ville Syrjälä
2021-10-14 17:45 ` Ville Syrjälä
2021-10-14 18:01 ` Borislav Petkov
2021-10-14 18:46 ` Ville Syrjälä
2021-10-14 19:08 ` Borislav Petkov [this message]
2021-10-15 11:04 ` Borislav Petkov
2021-10-16 7:26 ` Ser Olmy
2021-10-16 10:35 ` Borislav Petkov
2021-10-18 6:55 ` Ville Syrjälä
2021-10-14 14:44 ` Borislav Petkov
2021-10-16 12:22 ` [tip: x86/urgent] x86/fpu: Mask out the invalid MXCSR bits properly tip-bot2 for Borislav Petkov
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