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From: Greg KH <gregkh@linuxfoundation.org>
To: "David E. Box" <david.e.box@linux.intel.com>
Cc: lee.jones@linaro.org, hdegoede@redhat.com, bhelgaas@google.com,
	andriy.shevchenko@linux.intel.com, srinivas.pandruvada@intel.com,
	mgross@linux.intel.com, linux-kernel@vger.kernel.org,
	platform-driver-x86@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH 4/4] platform/x86: Add Intel Software Defined Silicon driver
Date: Sun, 21 Nov 2021 13:31:25 +0100	[thread overview]
Message-ID: <YZo8HUxx8LNgOMeK@kroah.com> (raw)
In-Reply-To: <20211120231705.189969-5-david.e.box@linux.intel.com>

On Sat, Nov 20, 2021 at 03:17:05PM -0800, David E. Box wrote:
> +static ssize_t registers_read(struct file *filp, struct kobject *kobj,
> +			      struct bin_attribute *attr, char *buf, loff_t off,
> +			      size_t count)
> +{
> +	struct device *dev = kobj_to_dev(kobj);
> +	struct sdsi_priv *priv = dev_get_drvdata(dev);
> +	void __iomem *addr = priv->regs_addr;
> +
> +	memcpy_fromio(buf, addr + off, count);

Oh nice, this will be fun if I provide "interesting" values for off to
the function right?

Remember:
	All input is evil.

> +
> +	return count;
> +}
> +static BIN_ATTR(registers, 0400, registers_read, NULL, SDSI_SIZE_REGS);
> +
> +static struct bin_attribute *sdsi_bin_attrs[] = {
> +	&bin_attr_registers,
> +	&bin_attr_state_certificate,
> +	&bin_attr_provision_akc,
> +	&bin_attr_provision_cap,
> +	NULL
> +};
> +
> +static ssize_t guid_show(struct device *dev, struct device_attribute *attr, char *buf)
> +{
> +	struct sdsi_priv *priv = dev_get_drvdata(dev);
> +
> +	return sprintf(buf, "0x%x\n", priv->guid);

sysfs_emit() please.

These sysfs attributes are crazy.  Who has audited them to be correct
and work properly?  It feels like there are just buffer overflows
waiting to be exploited in them due to the reading/writing of raw memory
buffers all over the place.

Where is the userspace tool that uses these files?

thanks,

greg k-h

  reply	other threads:[~2021-11-21 12:31 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-20 23:17 [PATCH 0/4] Auxiliary bus driver support for Intel PCIe VSEC/DVSEC David E. Box
2021-11-20 23:17 ` [PATCH 1/4] PCI: Add #defines for accessing PCIe DVSEC fields David E. Box
2021-11-21 12:24   ` Greg KH
2021-11-21 15:48     ` David E. Box
2021-11-22 18:28     ` Bjorn Helgaas
2021-11-20 23:17 ` [PATCH 2/4] driver core: auxiliary bus: Add driver data helpers David E. Box
2021-11-20 23:17 ` [PATCH 3/4] platform/x86/intel: Move intel_pmt from MFD to Auxiliary Bus David E. Box
2021-11-22 18:43   ` Bjorn Helgaas
2021-11-22 23:09     ` David E. Box
2021-11-20 23:17 ` [PATCH 4/4] platform/x86: Add Intel Software Defined Silicon driver David E. Box
2021-11-21 12:31   ` Greg KH [this message]
2021-11-21 17:18     ` David E. Box
2021-11-22  6:21       ` Greg KH
2021-11-22 14:51         ` David E. Box
2021-11-22 18:44   ` Bjorn Helgaas
2021-11-22 23:20     ` David E. Box

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