Re: Clause 45 and Clause 22 PHYs on one MDIO bus

[Andrew Lunn <andrew@lunn.ch>]

On Mon, Mar 21, 2022 at 12:21:48PM +0100, Michael Walle wrote:
> Hi,
> 
> I have a board with a c22 phy (microchip lan8814) and a c45 phy
> (intel/maxlinear gyp215) on one bus. If I understand it correctly, both
> accesses should be able to coexist on one bus.

Yes. A C22 PHY should ignore a C45 access and vica versa.

> But the microchip lan8814
> actually has a bug and gets confused by c45 accesses. For example it will
> respond in the middle of another transaction with its own data if it
> decodes it as a read. That is something we can see on a logic analyzer.
> But we also see random register writes on the lan8814 (which you don't see
> on the logic analyzer obviously). Fortunately, the GPY215 supports indirect
> MMD access by the standard c22 registers. Thus as a workaround for the
> problem, we could have a c22 only mdio bus.

That should work, but you loose some performance.

> The SoC I'm using is the LAN9668, which uses the mdio-mscc-mdio driver.
> First problem there, it doesn't support C45 (yet) but also doesn't check
> for MII_ADDR_C45 and happily reads/writes bogus registers.

There are many drivers like that :-(

Whenever a new driver is posted, it is one of the things i ask
for. But older drivers are missing such checks.

> I've looked at the mdio subsystem in linux, there is probe_capabilities
> (MDIOBUS_C45 and friends) but the mxl-gpy.c is using c45 accesses
> nevertheless. I'm not sure if this is a bug or not.

No, that is not a bug. The PHY driver knows the device should be c45
capable. So it will use C45 addresses. The phydev->is_c45 should
indicate if it is possible to perform c45 transactions to the PHY. If
it is not, the core will make use of indirect access via C22,
otherwise the core will perform a direct C45 access.

So it seems like all you need to do is make mdio-mscc-mdio return
-EOPNOTSUPP for C45 and check that phydev->is_c45 is correctly false.

	   Andrew