From: Mark Brown <broonie@kernel.org>
To: Christophe Leroy <christophe.leroy@csgroup.eu>
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH v3] spi: Add capability to perform some transfer with chipselect off
Date: Wed, 7 Sep 2022 12:44:16 +0100 [thread overview]
Message-ID: <YxiEEP3krNUiUvlg@sirena.org.uk> (raw)
In-Reply-To: <fabbc87627e5ddc2c913b368ae99386668d8dcfb.1660830866.git.christophe.leroy@csgroup.eu>
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On Thu, Aug 18, 2022 at 03:57:49PM +0200, Christophe Leroy wrote:
> Some components require a few clock cycles with chipselect off before
> or/and after the data transfer done with CS on.
>
> Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK
> should have one cycle before CS goes low, and two cycles after
> CS goes high".
This doesn't apply against current code, please check and resend.
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next prev parent reply other threads:[~2022-09-07 11:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 13:57 Christophe Leroy
2022-09-07 11:44 ` Mark Brown [this message]
2022-09-07 14:15 ` Christophe Leroy
2022-09-07 15:12 ` Mark Brown
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