From: Christophe Leroy <christophe.leroy@csgroup.eu>
To: Mark Brown <broonie@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>
Subject: Re: [PATCH v3] spi: Add capability to perform some transfer with chipselect off
Date: Wed, 7 Sep 2022 14:15:40 +0000 [thread overview]
Message-ID: <b8f85b72-5313-affb-3402-70e2102d1383@csgroup.eu> (raw)
In-Reply-To: <YxiEEP3krNUiUvlg@sirena.org.uk>
Le 07/09/2022 à 13:44, Mark Brown a écrit :
> On Thu, Aug 18, 2022 at 03:57:49PM +0200, Christophe Leroy wrote:
>> Some components require a few clock cycles with chipselect off before
>> or/and after the data transfer done with CS on.
>>
>> Typically IDT 801034 QUAD PCM CODEC datasheet states "Note *: CCLK
>> should have one cycle before CS goes low, and two cycles after
>> CS goes high".
>
> This doesn't apply against current code, please check and resend.
Looks like my patch was from before the percpu statistics.
I just sent a rebased patch.
Christophe
next prev parent reply other threads:[~2022-09-07 14:15 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-18 13:57 Christophe Leroy
2022-09-07 11:44 ` Mark Brown
2022-09-07 14:15 ` Christophe Leroy [this message]
2022-09-07 15:12 ` Mark Brown
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