* [PATCH v1 1/3] pinctrl: tangier: Introduce Intel Tangier driver
2023-08-14 5:40 [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver Raag Jadav
@ 2023-08-14 5:40 ` Raag Jadav
2023-08-14 5:40 ` [PATCH v1 2/3] pinctrl: merrifield: Adapt to " Raag Jadav
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Raag Jadav @ 2023-08-14 5:40 UTC (permalink / raw)
To: linus.walleij, mika.westerberg, andriy.shevchenko
Cc: linux-gpio, linux-kernel, mallikarjunappa.sangannavar, pandith.n,
Raag Jadav
Intel Tangier implements the common pinctrl functionalities for
Merrifield and Moorefield platforms.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/pinctrl/intel/Kconfig | 1 +
drivers/pinctrl/intel/Kconfig.tng | 17 +
drivers/pinctrl/intel/Makefile | 1 +
drivers/pinctrl/intel/pinctrl-tangier.c | 589 ++++++++++++++++++++++++
drivers/pinctrl/intel/pinctrl-tangier.h | 92 ++++
5 files changed, 700 insertions(+)
create mode 100644 drivers/pinctrl/intel/Kconfig.tng
create mode 100644 drivers/pinctrl/intel/pinctrl-tangier.c
create mode 100644 drivers/pinctrl/intel/pinctrl-tangier.h
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index b3ec00624416..f2bdb0726e31 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -187,4 +187,5 @@ config PINCTRL_TIGERLAKE
This pinctrl driver provides an interface that allows configuring
of Intel Tiger Lake PCH pins and using them as GPIOs.
+source "drivers/pinctrl/intel/Kconfig.tng"
endmenu
diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng
new file mode 100644
index 000000000000..8d7757913b21
--- /dev/null
+++ b/drivers/pinctrl/intel/Kconfig.tng
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+# Intel Tangier and compatible pin control drivers
+
+if X86_INTEL_MID || COMPILE_TEST
+
+config PINCTRL_TANGIER
+ tristate
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ help
+ This is a library driver for Intel Tangier pin controller and to
+ be selected and used by respective compatible platform drivers.
+
+ If built as a module its name will be pinctrl-tangier.
+
+endif
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 906dd6c8d837..f6d30f2d973a 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
obj-$(CONFIG_PINCTRL_LYNXPOINT) += pinctrl-lynxpoint.o
+obj-$(CONFIG_PINCTRL_TANGIER) += pinctrl-tangier.o
obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_MOOREFIELD) += pinctrl-moorefield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
diff --git a/drivers/pinctrl/intel/pinctrl-tangier.c b/drivers/pinctrl/intel/pinctrl-tangier.c
new file mode 100644
index 000000000000..40dd60c9e526
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-tangier.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Tangier pinctrl driver
+ *
+ * Copyright (C) 2016, 2023 Intel Corporation
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ * Raag Jadav <raag.jadav@intel.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/export.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/overflow.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "../core.h"
+#include "pinctrl-intel.h"
+#include "pinctrl-tangier.h"
+
+#define SLEW_OFFSET 0x000
+#define BUFCFG_OFFSET 0x100
+#define MISC_OFFSET 0x300
+
+#define BUFCFG_PINMODE_SHIFT 0
+#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
+#define BUFCFG_PINMODE_GPIO 0
+#define BUFCFG_PUPD_VAL_SHIFT 4
+#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
+#define BUFCFG_PUPD_VAL_2K 0
+#define BUFCFG_PUPD_VAL_20K 1
+#define BUFCFG_PUPD_VAL_50K 2
+#define BUFCFG_PUPD_VAL_910 3
+#define BUFCFG_PU_EN BIT(8)
+#define BUFCFG_PD_EN BIT(9)
+#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
+#define BUFCFG_SLEWSEL BIT(10)
+#define BUFCFG_OVINEN BIT(12)
+#define BUFCFG_OVINEN_EN BIT(13)
+#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
+#define BUFCFG_OVOUTEN BIT(14)
+#define BUFCFG_OVOUTEN_EN BIT(15)
+#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
+#define BUFCFG_INDATAOV_VAL BIT(16)
+#define BUFCFG_INDATAOV_EN BIT(17)
+#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
+#define BUFCFG_OUTDATAOV_VAL BIT(18)
+#define BUFCFG_OUTDATAOV_EN BIT(19)
+#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
+#define BUFCFG_OD_EN BIT(21)
+
+#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
+
+static const struct tng_family *tng_get_family(struct tng_pinctrl *tp,
+ unsigned int pin)
+{
+ const struct tng_family *family;
+ unsigned int i;
+
+ for (i = 0; i < tp->nfamilies; i++) {
+ family = &tp->families[i];
+ if (pin >= family->pin_base &&
+ pin < family->pin_base + family->npins)
+ return family;
+ }
+
+ dev_warn(tp->dev, "failed to find family for pin %u\n", pin);
+ return NULL;
+}
+
+static bool tng_buf_available(struct tng_pinctrl *tp, unsigned int pin)
+{
+ const struct tng_family *family;
+
+ family = tng_get_family(tp, pin);
+ if (!family)
+ return false;
+
+ return !family->protected;
+}
+
+static void __iomem *tng_get_bufcfg(struct tng_pinctrl *tp, unsigned int pin)
+{
+ const struct tng_family *family;
+ unsigned int bufno;
+
+ family = tng_get_family(tp, pin);
+ if (!family)
+ return NULL;
+
+ bufno = pin_to_bufno(family, pin);
+ return family->regs + BUFCFG_OFFSET + bufno * 4;
+}
+
+static int tng_read_bufcfg(struct tng_pinctrl *tp, unsigned int pin, u32 *value)
+{
+ void __iomem *bufcfg;
+
+ if (!tng_buf_available(tp, pin))
+ return -EBUSY;
+
+ bufcfg = tng_get_bufcfg(tp, pin);
+ *value = readl(bufcfg);
+
+ return 0;
+}
+
+static void tng_update_bufcfg(struct tng_pinctrl *tp, unsigned int pin,
+ u32 bits, u32 mask)
+{
+ void __iomem *bufcfg;
+ u32 value;
+
+ bufcfg = tng_get_bufcfg(tp, pin);
+
+ value = readl(bufcfg);
+ value = (value & ~mask) | (bits & mask);
+ writel(value, bufcfg);
+}
+
+static int tng_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+
+ return tp->ngroups;
+}
+
+static const char *tng_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int group)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+
+ return tp->groups[group].grp.name;
+}
+
+static int tng_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
+ const unsigned int **pins, unsigned int *npins)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = tp->groups[group].grp.pins;
+ *npins = tp->groups[group].grp.npins;
+ return 0;
+}
+
+static void tng_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
+ unsigned int pin)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+ u32 value, mode;
+ int ret;
+
+ ret = tng_read_bufcfg(tp, pin, &value);
+ if (ret) {
+ seq_puts(s, "not available");
+ return;
+ }
+
+ mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
+ if (mode == BUFCFG_PINMODE_GPIO)
+ seq_puts(s, "GPIO ");
+ else
+ seq_printf(s, "mode %d ", mode);
+
+ seq_printf(s, "0x%08x", value);
+}
+
+static const struct pinctrl_ops tng_pinctrl_ops = {
+ .get_groups_count = tng_get_groups_count,
+ .get_group_name = tng_get_group_name,
+ .get_group_pins = tng_get_group_pins,
+ .pin_dbg_show = tng_pin_dbg_show,
+};
+
+static int tng_get_functions_count(struct pinctrl_dev *pctldev)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+
+ return tp->nfunctions;
+}
+
+static const char *tng_get_function_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+
+ return tp->functions[function].func.name;
+}
+
+static int tng_get_function_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned int * const ngroups)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+
+ *groups = tp->functions[function].func.groups;
+ *ngroups = tp->functions[function].func.ngroups;
+ return 0;
+}
+
+static int tng_pinmux_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+ const struct intel_pingroup *grp = &tp->groups[group];
+ u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
+ u32 mask = BUFCFG_PINMODE_MASK;
+ unsigned long flags;
+ unsigned int i;
+
+ /*
+ * All pins in the groups needs to be accessible and writable
+ * before we can enable the mux for this group.
+ */
+ for (i = 0; i < grp->grp.npins; i++) {
+ if (!tng_buf_available(tp, grp->grp.pins[i]))
+ return -EBUSY;
+ }
+
+ /* Now enable the mux setting for each pin in the group */
+ raw_spin_lock_irqsave(&tp->lock, flags);
+ for (i = 0; i < grp->grp.npins; i++)
+ tng_update_bufcfg(tp, grp->grp.pins[i], bits, mask);
+ raw_spin_unlock_irqrestore(&tp->lock, flags);
+
+ return 0;
+}
+
+static int tng_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+ u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
+ u32 mask = BUFCFG_PINMODE_MASK;
+ unsigned long flags;
+
+ if (!tng_buf_available(tp, pin))
+ return -EBUSY;
+
+ raw_spin_lock_irqsave(&tp->lock, flags);
+ tng_update_bufcfg(tp, pin, bits, mask);
+ raw_spin_unlock_irqrestore(&tp->lock, flags);
+
+ return 0;
+}
+
+static const struct pinmux_ops tng_pinmux_ops = {
+ .get_functions_count = tng_get_functions_count,
+ .get_function_name = tng_get_function_name,
+ .get_function_groups = tng_get_function_groups,
+ .set_mux = tng_pinmux_set_mux,
+ .gpio_request_enable = tng_gpio_request_enable,
+};
+
+static int tng_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *config)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+ u32 value, term;
+ u16 arg = 0;
+ int ret;
+
+ ret = tng_read_bufcfg(tp, pin, &value);
+ if (ret)
+ return -ENOTSUPP;
+
+ term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ if (value & BUFCFG_Px_EN_MASK)
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
+ return -EINVAL;
+
+ switch (term) {
+ case BUFCFG_PUPD_VAL_910:
+ arg = 910;
+ break;
+ case BUFCFG_PUPD_VAL_2K:
+ arg = 2000;
+ break;
+ case BUFCFG_PUPD_VAL_20K:
+ arg = 20000;
+ break;
+ case BUFCFG_PUPD_VAL_50K:
+ arg = 50000;
+ break;
+ }
+
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
+ return -EINVAL;
+
+ switch (term) {
+ case BUFCFG_PUPD_VAL_910:
+ arg = 910;
+ break;
+ case BUFCFG_PUPD_VAL_2K:
+ arg = 2000;
+ break;
+ case BUFCFG_PUPD_VAL_20K:
+ arg = 20000;
+ break;
+ case BUFCFG_PUPD_VAL_50K:
+ arg = 50000;
+ break;
+ }
+
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ if (value & BUFCFG_OD_EN)
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ if (!(value & BUFCFG_OD_EN))
+ return -EINVAL;
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ if (value & BUFCFG_SLEWSEL)
+ arg = 1;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, arg);
+ return 0;
+}
+
+static int tng_config_set_pin(struct tng_pinctrl *tp, unsigned int pin,
+ unsigned long config)
+{
+ unsigned int param = pinconf_to_config_param(config);
+ unsigned int arg = pinconf_to_config_argument(config);
+ u32 mask, term, value = 0;
+ unsigned long flags;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_UP:
+ /* Set default strength value in case none is given */
+ if (arg == 1)
+ arg = 20000;
+
+ switch (arg) {
+ case 50000:
+ term = BUFCFG_PUPD_VAL_50K;
+ break;
+ case 20000:
+ term = BUFCFG_PUPD_VAL_20K;
+ break;
+ case 2000:
+ term = BUFCFG_PUPD_VAL_2K;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
+ value = BUFCFG_PU_EN | (term << BUFCFG_PUPD_VAL_SHIFT);
+ break;
+
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ /* Set default strength value in case none is given */
+ if (arg == 1)
+ arg = 20000;
+
+ switch (arg) {
+ case 50000:
+ term = BUFCFG_PUPD_VAL_50K;
+ break;
+ case 20000:
+ term = BUFCFG_PUPD_VAL_20K;
+ break;
+ case 2000:
+ term = BUFCFG_PUPD_VAL_2K;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mask = BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
+ value = BUFCFG_PD_EN | (term << BUFCFG_PUPD_VAL_SHIFT);
+ break;
+
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ mask = BUFCFG_OD_EN;
+ break;
+
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ mask = BUFCFG_OD_EN;
+ value = BUFCFG_OD_EN;
+ break;
+
+ case PIN_CONFIG_SLEW_RATE:
+ mask = BUFCFG_SLEWSEL;
+ if (arg)
+ value = BUFCFG_SLEWSEL;
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ raw_spin_lock_irqsave(&tp->lock, flags);
+ tng_update_bufcfg(tp, pin, value, mask);
+ raw_spin_unlock_irqrestore(&tp->lock, flags);
+
+ return 0;
+}
+
+static int tng_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int nconfigs)
+{
+ struct tng_pinctrl *tp = pinctrl_dev_get_drvdata(pctldev);
+ unsigned int i;
+ int ret;
+
+ if (!tng_buf_available(tp, pin))
+ return -ENOTSUPP;
+
+ for (i = 0; i < nconfigs; i++) {
+ switch (pinconf_to_config_param(configs[i])) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+ case PIN_CONFIG_SLEW_RATE:
+ ret = tng_config_set_pin(tp, pin, configs[i]);
+ if (ret)
+ return ret;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+ }
+
+ return 0;
+}
+
+static int tng_config_group_get(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *config)
+{
+ const unsigned int *pins;
+ unsigned int npins;
+ int ret;
+
+ ret = tng_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+
+ return tng_config_get(pctldev, pins[0], config);
+}
+
+static int tng_config_group_set(struct pinctrl_dev *pctldev,
+ unsigned int group, unsigned long *configs,
+ unsigned int num_configs)
+{
+ const unsigned int *pins;
+ unsigned int npins;
+ int i, ret;
+
+ ret = tng_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < npins; i++) {
+ ret = tng_config_set(pctldev, pins[i], configs, num_configs);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct pinconf_ops tng_pinconf_ops = {
+ .is_generic = true,
+ .pin_config_get = tng_config_get,
+ .pin_config_set = tng_config_set,
+ .pin_config_group_get = tng_config_group_get,
+ .pin_config_group_set = tng_config_group_set,
+};
+
+static const struct pinctrl_desc tng_pinctrl_desc = {
+ .pctlops = &tng_pinctrl_ops,
+ .pmxops = &tng_pinmux_ops,
+ .confops = &tng_pinconf_ops,
+ .owner = THIS_MODULE,
+};
+
+static int tng_pinctrl_probe(struct platform_device *pdev,
+ const struct tng_pinctrl *data)
+{
+ struct device *dev = &pdev->dev;
+ struct tng_family *families;
+ struct tng_pinctrl *tp;
+ size_t families_len;
+ void __iomem *regs;
+ unsigned int i;
+
+ tp = devm_kmemdup(dev, data, sizeof(*data), GFP_KERNEL);
+ if (!tp)
+ return -ENOMEM;
+
+ tp->dev = dev;
+ raw_spin_lock_init(&tp->lock);
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ /*
+ * Make a copy of the families which we can use to hold pointers
+ * to the registers.
+ */
+ families_len = size_mul(sizeof(*families), tp->nfamilies);
+ families = devm_kmemdup(dev, tp->families, families_len, GFP_KERNEL);
+ if (!families)
+ return -ENOMEM;
+
+ /* Splice memory resource by chunk per family */
+ for (i = 0; i < tp->nfamilies; i++) {
+ struct tng_family *family = &families[i];
+
+ family->regs = regs + family->barno * TNG_FAMILY_LEN;
+ }
+
+ tp->families = families;
+ tp->pctldesc = tng_pinctrl_desc;
+ tp->pctldesc.name = dev_name(dev);
+ tp->pctldesc.pins = tp->pins;
+ tp->pctldesc.npins = tp->npins;
+
+ tp->pctldev = devm_pinctrl_register(dev, &tp->pctldesc, tp);
+ if (IS_ERR(tp->pctldev))
+ return dev_err_probe(dev, PTR_ERR(tp->pctldev),
+ "failed to register pinctrl driver\n");
+
+ return 0;
+}
+
+int devm_tng_pinctrl_probe(struct platform_device *pdev)
+{
+ const struct tng_pinctrl *data;
+
+ data = device_get_match_data(&pdev->dev);
+ if (!data)
+ return -ENODATA;
+
+ return tng_pinctrl_probe(pdev, data);
+}
+EXPORT_SYMBOL_NS_GPL(devm_tng_pinctrl_probe, PINCTRL_TANGIER);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>");
+MODULE_DESCRIPTION("Intel Tangier pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/intel/pinctrl-tangier.h b/drivers/pinctrl/intel/pinctrl-tangier.h
new file mode 100644
index 000000000000..955cc967c0bc
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-tangier.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Intel Tangier pinctrl functions
+ *
+ * Copyright (C) 2016, 2023 Intel Corporation
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ * Raag Jadav <raag.jadav@intel.com>
+ */
+
+#ifndef PINCTRL_TANGIER_H
+#define PINCTRL_TANGIER_H
+
+#include <linux/spinlock_types.h>
+#include <linux/types.h>
+
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-intel.h"
+
+struct device;
+struct platform_device;
+
+#define TNG_FAMILY_NR 64
+#define TNG_FAMILY_LEN 0x400
+
+/**
+ * struct tng_family - Tangier pin family description
+ * @barno: MMIO BAR number where registers for this family reside
+ * @pin_base: Starting pin of pins in this family
+ * @npins: Number of pins in this family
+ * @protected: True if family is protected by access
+ * @regs: Family specific common registers
+ */
+struct tng_family {
+ unsigned int barno;
+ unsigned int pin_base;
+ size_t npins;
+ bool protected;
+ void __iomem *regs;
+};
+
+#define TNG_FAMILY(b, s, e) \
+ { \
+ .barno = (b), \
+ .pin_base = (s), \
+ .npins = (e) - (s) + 1, \
+ }
+
+#define TNG_FAMILY_PROTECTED(b, s, e) \
+ { \
+ .barno = (b), \
+ .pin_base = (s), \
+ .npins = (e) - (s) + 1, \
+ .protected = true, \
+ }
+
+/**
+ * struct tng_pinctrl - Tangier pinctrl private structure
+ * @dev: Pointer to the device structure
+ * @lock: Lock to serialize register access
+ * @pctldesc: Pin controller description
+ * @pctldev: Pointer to the pin controller device
+ * @families: Array of families this pinctrl handles
+ * @nfamilies: Number of families in the array
+ * @functions: Array of functions
+ * @nfunctions: Number of functions in the array
+ * @groups: Array of pin groups
+ * @ngroups: Number of groups in the array
+ * @pins: Array of pins this pinctrl controls
+ * @npins: Number of pins in the array
+ */
+struct tng_pinctrl {
+ struct device *dev;
+ raw_spinlock_t lock;
+ struct pinctrl_desc pctldesc;
+ struct pinctrl_dev *pctldev;
+
+ /* Pin controller configuration */
+ const struct tng_family *families;
+ size_t nfamilies;
+ const struct intel_function *functions;
+ size_t nfunctions;
+ const struct intel_pingroup *groups;
+ size_t ngroups;
+ const struct pinctrl_pin_desc *pins;
+ size_t npins;
+};
+
+int devm_tng_pinctrl_probe(struct platform_device *pdev);
+
+#endif /* PINCTRL_TANGIER_H */
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v1 2/3] pinctrl: merrifield: Adapt to Intel Tangier driver
2023-08-14 5:40 [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver Raag Jadav
2023-08-14 5:40 ` [PATCH v1 1/3] pinctrl: tangier: Introduce Intel Tangier driver Raag Jadav
@ 2023-08-14 5:40 ` Raag Jadav
2023-08-14 5:40 ` [PATCH v1 3/3] pinctrl: moorefield: " Raag Jadav
2023-08-15 13:01 ` [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver Andy Shevchenko
3 siblings, 0 replies; 5+ messages in thread
From: Raag Jadav @ 2023-08-14 5:40 UTC (permalink / raw)
To: linus.walleij, mika.westerberg, andriy.shevchenko
Cc: linux-gpio, linux-kernel, mallikarjunappa.sangannavar, pandith.n,
Raag Jadav
Make use of Intel Tangier as a library driver for Merrifield.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/pinctrl/intel/Kconfig | 11 -
drivers/pinctrl/intel/Kconfig.tng | 8 +
drivers/pinctrl/intel/pinctrl-merrifield.c | 677 +--------------------
3 files changed, 41 insertions(+), 655 deletions(-)
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index f2bdb0726e31..4042d6cbafcb 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -36,17 +36,6 @@ config PINCTRL_LYNXPOINT
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
-config PINCTRL_MERRIFIELD
- tristate "Intel Merrifield pinctrl driver"
- depends on X86_INTEL_MID
- select PINMUX
- select PINCONF
- select GENERIC_PINCONF
- help
- Merrifield Family-Level Interface Shim (FLIS) driver provides an
- interface that allows configuring of SoC pins and using them as
- GPIOs.
-
config PINCTRL_MOOREFIELD
tristate "Intel Moorefield pinctrl driver"
depends on X86_INTEL_MID
diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng
index 8d7757913b21..8a6d315e34d7 100644
--- a/drivers/pinctrl/intel/Kconfig.tng
+++ b/drivers/pinctrl/intel/Kconfig.tng
@@ -14,4 +14,12 @@ config PINCTRL_TANGIER
If built as a module its name will be pinctrl-tangier.
+config PINCTRL_MERRIFIELD
+ tristate "Intel Merrifield pinctrl driver"
+ select PINCTRL_TANGIER
+ help
+ Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
+ an interface that allows configuring of SoC pins and using them as
+ GPIOs.
+
endif
diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c
index fb6de38b1c50..d809680a09c9 100644
--- a/drivers/pinctrl/intel/pinctrl-merrifield.c
+++ b/drivers/pinctrl/intel/pinctrl-merrifield.c
@@ -6,85 +6,17 @@
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
-#include <linux/bits.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/seq_file.h>
+#include <linux/types.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
#include "pinctrl-intel.h"
-
-#define MRFLD_FAMILY_NR 64
-#define MRFLD_FAMILY_LEN 0x400
-
-#define SLEW_OFFSET 0x000
-#define BUFCFG_OFFSET 0x100
-#define MISC_OFFSET 0x300
-
-#define BUFCFG_PINMODE_SHIFT 0
-#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
-#define BUFCFG_PINMODE_GPIO 0
-#define BUFCFG_PUPD_VAL_SHIFT 4
-#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
-#define BUFCFG_PUPD_VAL_2K 0
-#define BUFCFG_PUPD_VAL_20K 1
-#define BUFCFG_PUPD_VAL_50K 2
-#define BUFCFG_PUPD_VAL_910 3
-#define BUFCFG_PU_EN BIT(8)
-#define BUFCFG_PD_EN BIT(9)
-#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
-#define BUFCFG_SLEWSEL BIT(10)
-#define BUFCFG_OVINEN BIT(12)
-#define BUFCFG_OVINEN_EN BIT(13)
-#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
-#define BUFCFG_OVOUTEN BIT(14)
-#define BUFCFG_OVOUTEN_EN BIT(15)
-#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
-#define BUFCFG_INDATAOV_VAL BIT(16)
-#define BUFCFG_INDATAOV_EN BIT(17)
-#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
-#define BUFCFG_OUTDATAOV_VAL BIT(18)
-#define BUFCFG_OUTDATAOV_EN BIT(19)
-#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
-#define BUFCFG_OD_EN BIT(21)
-
-/**
- * struct mrfld_family - Intel pin family description
- * @barno: MMIO BAR number where registers for this family reside
- * @pin_base: Starting pin of pins in this family
- * @npins: Number of pins in this family
- * @protected: True if family is protected by access
- * @regs: family specific common registers
- */
-struct mrfld_family {
- unsigned int barno;
- unsigned int pin_base;
- size_t npins;
- bool protected;
- void __iomem *regs;
-};
-
-#define MRFLD_FAMILY(b, s, e) \
- { \
- .barno = (b), \
- .pin_base = (s), \
- .npins = (e) - (s) + 1, \
- }
-
-#define MRFLD_FAMILY_PROTECTED(b, s, e) \
- { \
- .barno = (b), \
- .pin_base = (s), \
- .npins = (e) - (s) + 1, \
- .protected = true, \
- }
+#include "pinctrl-tangier.h"
static const struct pinctrl_pin_desc mrfld_pins[] = {
/* Family 0: OCP2SSC (0 pins) */
@@ -389,587 +321,43 @@ static const struct intel_function mrfld_functions[] = {
FUNCTION("pwm3", mrfld_pwm3_groups),
};
-static const struct mrfld_family mrfld_families[] = {
- MRFLD_FAMILY(1, 0, 12),
- MRFLD_FAMILY(2, 13, 36),
- MRFLD_FAMILY(3, 37, 56),
- MRFLD_FAMILY(4, 57, 64),
- MRFLD_FAMILY(5, 65, 78),
- MRFLD_FAMILY(6, 79, 100),
- MRFLD_FAMILY_PROTECTED(7, 101, 114),
- MRFLD_FAMILY(8, 115, 126),
- MRFLD_FAMILY(9, 127, 145),
- MRFLD_FAMILY(10, 146, 157),
- MRFLD_FAMILY(11, 158, 179),
- MRFLD_FAMILY_PROTECTED(12, 180, 194),
- MRFLD_FAMILY(13, 195, 214),
- MRFLD_FAMILY(14, 215, 227),
- MRFLD_FAMILY(15, 228, 232),
+static const struct tng_family mrfld_families[] = {
+ TNG_FAMILY(1, 0, 12),
+ TNG_FAMILY(2, 13, 36),
+ TNG_FAMILY(3, 37, 56),
+ TNG_FAMILY(4, 57, 64),
+ TNG_FAMILY(5, 65, 78),
+ TNG_FAMILY(6, 79, 100),
+ TNG_FAMILY_PROTECTED(7, 101, 114),
+ TNG_FAMILY(8, 115, 126),
+ TNG_FAMILY(9, 127, 145),
+ TNG_FAMILY(10, 146, 157),
+ TNG_FAMILY(11, 158, 179),
+ TNG_FAMILY_PROTECTED(12, 180, 194),
+ TNG_FAMILY(13, 195, 214),
+ TNG_FAMILY(14, 215, 227),
+ TNG_FAMILY(15, 228, 232),
};
-/**
- * struct mrfld_pinctrl - Intel Merrifield pinctrl private structure
- * @dev: Pointer to the device structure
- * @lock: Lock to serialize register access
- * @pctldesc: Pin controller description
- * @pctldev: Pointer to the pin controller device
- * @families: Array of families this pinctrl handles
- * @nfamilies: Number of families in the array
- * @functions: Array of functions
- * @nfunctions: Number of functions in the array
- * @groups: Array of pin groups
- * @ngroups: Number of groups in the array
- * @pins: Array of pins this pinctrl controls
- * @npins: Number of pins in the array
- */
-struct mrfld_pinctrl {
- struct device *dev;
- raw_spinlock_t lock;
- struct pinctrl_desc pctldesc;
- struct pinctrl_dev *pctldev;
-
- /* Pin controller configuration */
- const struct mrfld_family *families;
- size_t nfamilies;
- const struct intel_function *functions;
- size_t nfunctions;
- const struct intel_pingroup *groups;
- size_t ngroups;
- const struct pinctrl_pin_desc *pins;
- size_t npins;
-};
-
-#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
-
-static const struct mrfld_family *mrfld_get_family(struct mrfld_pinctrl *mp,
- unsigned int pin)
-{
- const struct mrfld_family *family;
- unsigned int i;
-
- for (i = 0; i < mp->nfamilies; i++) {
- family = &mp->families[i];
- if (pin >= family->pin_base &&
- pin < family->pin_base + family->npins)
- return family;
- }
-
- dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
- return NULL;
-}
-
-static bool mrfld_buf_available(struct mrfld_pinctrl *mp, unsigned int pin)
-{
- const struct mrfld_family *family;
-
- family = mrfld_get_family(mp, pin);
- if (!family)
- return false;
-
- return !family->protected;
-}
-
-static void __iomem *mrfld_get_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin)
-{
- const struct mrfld_family *family;
- unsigned int bufno;
-
- family = mrfld_get_family(mp, pin);
- if (!family)
- return NULL;
-
- bufno = pin_to_bufno(family, pin);
- return family->regs + BUFCFG_OFFSET + bufno * 4;
-}
-
-static int mrfld_read_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin, u32 *value)
-{
- void __iomem *bufcfg;
-
- if (!mrfld_buf_available(mp, pin))
- return -EBUSY;
-
- bufcfg = mrfld_get_bufcfg(mp, pin);
- *value = readl(bufcfg);
-
- return 0;
-}
-
-static void mrfld_update_bufcfg(struct mrfld_pinctrl *mp, unsigned int pin,
- u32 bits, u32 mask)
-{
- void __iomem *bufcfg;
- u32 value;
-
- bufcfg = mrfld_get_bufcfg(mp, pin);
- value = readl(bufcfg);
-
- value &= ~mask;
- value |= bits & mask;
-
- writel(value, bufcfg);
-}
-
-static int mrfld_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->ngroups;
-}
-
-static const char *mrfld_get_group_name(struct pinctrl_dev *pctldev,
- unsigned int group)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->groups[group].grp.name;
-}
-
-static int mrfld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
- const unsigned int **pins, unsigned int *npins)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- *pins = mp->groups[group].grp.pins;
- *npins = mp->groups[group].grp.npins;
- return 0;
-}
-
-static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned int pin)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- u32 value, mode;
- int ret;
-
- ret = mrfld_read_bufcfg(mp, pin, &value);
- if (ret) {
- seq_puts(s, "not available");
- return;
- }
-
- mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
- if (mode == BUFCFG_PINMODE_GPIO)
- seq_puts(s, "GPIO ");
- else
- seq_printf(s, "mode %d ", mode);
-
- seq_printf(s, "0x%08x", value);
-}
-
-static const struct pinctrl_ops mrfld_pinctrl_ops = {
- .get_groups_count = mrfld_get_groups_count,
- .get_group_name = mrfld_get_group_name,
- .get_group_pins = mrfld_get_group_pins,
- .pin_dbg_show = mrfld_pin_dbg_show,
-};
-
-static int mrfld_get_functions_count(struct pinctrl_dev *pctldev)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->nfunctions;
-}
-
-static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
- unsigned int function)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->functions[function].func.name;
-}
-
-static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
- unsigned int function,
- const char * const **groups,
- unsigned int * const ngroups)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = mp->functions[function].func.groups;
- *ngroups = mp->functions[function].func.ngroups;
- return 0;
-}
-
-static int mrfld_pinmux_set_mux(struct pinctrl_dev *pctldev,
- unsigned int function,
- unsigned int group)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- const struct intel_pingroup *grp = &mp->groups[group];
- u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
- u32 mask = BUFCFG_PINMODE_MASK;
- unsigned long flags;
- unsigned int i;
-
- /*
- * All pins in the groups needs to be accessible and writable
- * before we can enable the mux for this group.
- */
- for (i = 0; i < grp->grp.npins; i++) {
- if (!mrfld_buf_available(mp, grp->grp.pins[i]))
- return -EBUSY;
- }
-
- /* Now enable the mux setting for each pin in the group */
- raw_spin_lock_irqsave(&mp->lock, flags);
- for (i = 0; i < grp->grp.npins; i++)
- mrfld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
- raw_spin_unlock_irqrestore(&mp->lock, flags);
-
- return 0;
-}
-
-static int mrfld_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int pin)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
- u32 mask = BUFCFG_PINMODE_MASK;
- unsigned long flags;
-
- if (!mrfld_buf_available(mp, pin))
- return -EBUSY;
-
- raw_spin_lock_irqsave(&mp->lock, flags);
- mrfld_update_bufcfg(mp, pin, bits, mask);
- raw_spin_unlock_irqrestore(&mp->lock, flags);
-
- return 0;
-}
-
-static const struct pinmux_ops mrfld_pinmux_ops = {
- .get_functions_count = mrfld_get_functions_count,
- .get_function_name = mrfld_get_function_name,
- .get_function_groups = mrfld_get_function_groups,
- .set_mux = mrfld_pinmux_set_mux,
- .gpio_request_enable = mrfld_gpio_request_enable,
-};
-
-static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- u32 value, term;
- u16 arg = 0;
- int ret;
-
- ret = mrfld_read_bufcfg(mp, pin, &value);
- if (ret)
- return -ENOTSUPP;
-
- term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- if (value & BUFCFG_Px_EN_MASK)
- return -EINVAL;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
- return -EINVAL;
-
- switch (term) {
- case BUFCFG_PUPD_VAL_910:
- arg = 910;
- break;
- case BUFCFG_PUPD_VAL_2K:
- arg = 2000;
- break;
- case BUFCFG_PUPD_VAL_20K:
- arg = 20000;
- break;
- case BUFCFG_PUPD_VAL_50K:
- arg = 50000;
- break;
- }
-
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
- return -EINVAL;
-
- switch (term) {
- case BUFCFG_PUPD_VAL_910:
- arg = 910;
- break;
- case BUFCFG_PUPD_VAL_2K:
- arg = 2000;
- break;
- case BUFCFG_PUPD_VAL_20K:
- arg = 20000;
- break;
- case BUFCFG_PUPD_VAL_50K:
- arg = 50000;
- break;
- }
-
- break;
-
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- if (value & BUFCFG_OD_EN)
- return -EINVAL;
- break;
-
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- if (!(value & BUFCFG_OD_EN))
- return -EINVAL;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (!(value & BUFCFG_SLEWSEL))
- arg = 0;
- else
- arg = 1;
- break;
-
- default:
- return -ENOTSUPP;
- }
-
- *config = pinconf_to_config_packed(param, arg);
- return 0;
-}
-
-static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
- unsigned long config)
-{
- unsigned int param = pinconf_to_config_param(config);
- unsigned int arg = pinconf_to_config_argument(config);
- u32 bits = 0, mask = 0;
- unsigned long flags;
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
- bits |= BUFCFG_PU_EN;
-
- /* Set default strength value in case none is given */
- if (arg == 1)
- arg = 20000;
-
- switch (arg) {
- case 50000:
- bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 20000:
- bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 2000:
- bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- default:
- return -EINVAL;
- }
-
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
- bits |= BUFCFG_PD_EN;
-
- /* Set default strength value in case none is given */
- if (arg == 1)
- arg = 20000;
-
- switch (arg) {
- case 50000:
- bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 20000:
- bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 2000:
- bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- default:
- return -EINVAL;
- }
-
- break;
-
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- mask |= BUFCFG_OD_EN;
- bits &= ~BUFCFG_OD_EN;
- break;
-
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- mask |= BUFCFG_OD_EN;
- bits |= BUFCFG_OD_EN;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- mask |= BUFCFG_SLEWSEL;
- if (arg)
- bits |= BUFCFG_SLEWSEL;
- break;
- }
-
- raw_spin_lock_irqsave(&mp->lock, flags);
- mrfld_update_bufcfg(mp, pin, bits, mask);
- raw_spin_unlock_irqrestore(&mp->lock, flags);
-
- return 0;
-}
-
-static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *configs, unsigned int nconfigs)
-{
- struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- unsigned int i;
- int ret;
-
- if (!mrfld_buf_available(mp, pin))
- return -ENOTSUPP;
-
- for (i = 0; i < nconfigs; i++) {
- switch (pinconf_to_config_param(configs[i])) {
- case PIN_CONFIG_BIAS_DISABLE:
- case PIN_CONFIG_BIAS_PULL_UP:
- case PIN_CONFIG_BIAS_PULL_DOWN:
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- case PIN_CONFIG_SLEW_RATE:
- ret = mrfld_config_set_pin(mp, pin, configs[i]);
- if (ret)
- return ret;
- break;
-
- default:
- return -ENOTSUPP;
- }
- }
-
- return 0;
-}
-
-static int mrfld_config_group_get(struct pinctrl_dev *pctldev,
- unsigned int group, unsigned long *config)
-{
- const unsigned int *pins;
- unsigned int npins;
- int ret;
-
- ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
- if (ret)
- return ret;
-
- ret = mrfld_config_get(pctldev, pins[0], config);
- if (ret)
- return ret;
-
- return 0;
-}
-
-static int mrfld_config_group_set(struct pinctrl_dev *pctldev,
- unsigned int group, unsigned long *configs,
- unsigned int num_configs)
-{
- const unsigned int *pins;
- unsigned int npins;
- int i, ret;
-
- ret = mrfld_get_group_pins(pctldev, group, &pins, &npins);
- if (ret)
- return ret;
-
- for (i = 0; i < npins; i++) {
- ret = mrfld_config_set(pctldev, pins[i], configs, num_configs);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static const struct pinconf_ops mrfld_pinconf_ops = {
- .is_generic = true,
- .pin_config_get = mrfld_config_get,
- .pin_config_set = mrfld_config_set,
- .pin_config_group_get = mrfld_config_group_get,
- .pin_config_group_set = mrfld_config_group_set,
-};
-
-static const struct pinctrl_desc mrfld_pinctrl_desc = {
- .pctlops = &mrfld_pinctrl_ops,
- .pmxops = &mrfld_pinmux_ops,
- .confops = &mrfld_pinconf_ops,
- .owner = THIS_MODULE,
+static const struct tng_pinctrl mrfld_soc_data = {
+ .pins = mrfld_pins,
+ .npins = ARRAY_SIZE(mrfld_pins),
+ .groups = mrfld_groups,
+ .ngroups = ARRAY_SIZE(mrfld_groups),
+ .families = mrfld_families,
+ .nfamilies = ARRAY_SIZE(mrfld_families),
+ .functions = mrfld_functions,
+ .nfunctions = ARRAY_SIZE(mrfld_functions),
};
-static int mrfld_pinctrl_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct mrfld_family *families;
- struct mrfld_pinctrl *mp;
- void __iomem *regs;
- size_t nfamilies;
- unsigned int i;
-
- mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
- if (!mp)
- return -ENOMEM;
-
- mp->dev = dev;
- raw_spin_lock_init(&mp->lock);
-
- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
- return PTR_ERR(regs);
-
- /*
- * Make a copy of the families which we can use to hold pointers
- * to the registers.
- */
- nfamilies = ARRAY_SIZE(mrfld_families),
- families = devm_kmemdup(dev, mrfld_families, sizeof(mrfld_families), GFP_KERNEL);
- if (!families)
- return -ENOMEM;
-
- /* Splice memory resource by chunk per family */
- for (i = 0; i < nfamilies; i++) {
- struct mrfld_family *family = &families[i];
-
- family->regs = regs + family->barno * MRFLD_FAMILY_LEN;
- }
-
- mp->families = families;
- mp->nfamilies = nfamilies;
- mp->functions = mrfld_functions;
- mp->nfunctions = ARRAY_SIZE(mrfld_functions);
- mp->groups = mrfld_groups;
- mp->ngroups = ARRAY_SIZE(mrfld_groups);
- mp->pctldesc = mrfld_pinctrl_desc;
- mp->pctldesc.name = dev_name(dev);
- mp->pctldesc.pins = mrfld_pins;
- mp->pctldesc.npins = ARRAY_SIZE(mrfld_pins);
-
- mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp);
- if (IS_ERR(mp->pctldev)) {
- dev_err(dev, "failed to register pinctrl driver\n");
- return PTR_ERR(mp->pctldev);
- }
-
- platform_set_drvdata(pdev, mp);
- return 0;
-}
-
static const struct acpi_device_id mrfld_acpi_table[] = {
- { "INTC1002" },
+ { "INTC1002", (kernel_ulong_t)&mrfld_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mrfld_acpi_table);
static struct platform_driver mrfld_pinctrl_driver = {
- .probe = mrfld_pinctrl_probe,
+ .probe = devm_tng_pinctrl_probe,
.driver = {
.name = "pinctrl-merrifield",
.acpi_match_table = mrfld_acpi_table,
@@ -992,3 +380,4 @@ MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_DESCRIPTION("Intel Merrifield SoC pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:pinctrl-merrifield");
+MODULE_IMPORT_NS(PINCTRL_TANGIER);
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v1 3/3] pinctrl: moorefield: Adapt to Intel Tangier driver
2023-08-14 5:40 [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver Raag Jadav
2023-08-14 5:40 ` [PATCH v1 1/3] pinctrl: tangier: Introduce Intel Tangier driver Raag Jadav
2023-08-14 5:40 ` [PATCH v1 2/3] pinctrl: merrifield: Adapt to " Raag Jadav
@ 2023-08-14 5:40 ` Raag Jadav
2023-08-15 13:01 ` [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver Andy Shevchenko
3 siblings, 0 replies; 5+ messages in thread
From: Raag Jadav @ 2023-08-14 5:40 UTC (permalink / raw)
To: linus.walleij, mika.westerberg, andriy.shevchenko
Cc: linux-gpio, linux-kernel, mallikarjunappa.sangannavar, pandith.n,
Raag Jadav
Make use of Intel Tangier as a library driver for Moorefield.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
drivers/pinctrl/intel/Kconfig | 11 -
drivers/pinctrl/intel/Kconfig.tng | 8 +
drivers/pinctrl/intel/pinctrl-moorefield.c | 640 +--------------------
3 files changed, 37 insertions(+), 622 deletions(-)
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index 4042d6cbafcb..eaa45ebfd1c1 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -36,17 +36,6 @@ config PINCTRL_LYNXPOINT
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
-config PINCTRL_MOOREFIELD
- tristate "Intel Moorefield pinctrl driver"
- depends on X86_INTEL_MID
- select PINMUX
- select PINCONF
- select GENERIC_PINCONF
- help
- Moorefield Family-Level Interface Shim (FLIS) driver provides an
- interface that allows configuring of SoC pins and using them as
- GPIOs.
-
config PINCTRL_INTEL
tristate
select PINMUX
diff --git a/drivers/pinctrl/intel/Kconfig.tng b/drivers/pinctrl/intel/Kconfig.tng
index 8a6d315e34d7..6f88a64d260c 100644
--- a/drivers/pinctrl/intel/Kconfig.tng
+++ b/drivers/pinctrl/intel/Kconfig.tng
@@ -22,4 +22,12 @@ config PINCTRL_MERRIFIELD
an interface that allows configuring of SoC pins and using them as
GPIOs.
+config PINCTRL_MOOREFIELD
+ tristate "Intel Moorefield pinctrl driver"
+ select PINCTRL_TANGIER
+ help
+ Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
+ an interface that allows configuring of SoC pins and using them as
+ GPIOs.
+
endif
diff --git a/drivers/pinctrl/intel/pinctrl-moorefield.c b/drivers/pinctrl/intel/pinctrl-moorefield.c
index 2d38d953f360..807a694b818b 100644
--- a/drivers/pinctrl/intel/pinctrl-moorefield.c
+++ b/drivers/pinctrl/intel/pinctrl-moorefield.c
@@ -6,77 +6,16 @@
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
*/
-#include <linux/bits.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
+#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/seq_file.h>
+#include <linux/types.h>
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-#include "pinctrl-intel.h"
-
-#define MOFLD_FAMILY_NR 64
-#define MOFLD_FAMILY_LEN 0x400
-
-#define SLEW_OFFSET 0x000
-#define BUFCFG_OFFSET 0x100
-#define MISC_OFFSET 0x300
-
-#define BUFCFG_PINMODE_SHIFT 0
-#define BUFCFG_PINMODE_MASK GENMASK(2, 0)
-#define BUFCFG_PINMODE_GPIO 0
-#define BUFCFG_PUPD_VAL_SHIFT 4
-#define BUFCFG_PUPD_VAL_MASK GENMASK(5, 4)
-#define BUFCFG_PUPD_VAL_2K 0
-#define BUFCFG_PUPD_VAL_20K 1
-#define BUFCFG_PUPD_VAL_50K 2
-#define BUFCFG_PUPD_VAL_910 3
-#define BUFCFG_PU_EN BIT(8)
-#define BUFCFG_PD_EN BIT(9)
-#define BUFCFG_Px_EN_MASK GENMASK(9, 8)
-#define BUFCFG_SLEWSEL BIT(10)
-#define BUFCFG_OVINEN BIT(12)
-#define BUFCFG_OVINEN_EN BIT(13)
-#define BUFCFG_OVINEN_MASK GENMASK(13, 12)
-#define BUFCFG_OVOUTEN BIT(14)
-#define BUFCFG_OVOUTEN_EN BIT(15)
-#define BUFCFG_OVOUTEN_MASK GENMASK(15, 14)
-#define BUFCFG_INDATAOV_VAL BIT(16)
-#define BUFCFG_INDATAOV_EN BIT(17)
-#define BUFCFG_INDATAOV_MASK GENMASK(17, 16)
-#define BUFCFG_OUTDATAOV_VAL BIT(18)
-#define BUFCFG_OUTDATAOV_EN BIT(19)
-#define BUFCFG_OUTDATAOV_MASK GENMASK(19, 18)
-#define BUFCFG_OD_EN BIT(21)
-
-/**
- * struct mofld_family - Intel pin family description
- * @barno: MMIO BAR number where registers for this family reside
- * @pin_base: Starting pin of pins in this family
- * @npins: Number of pins in this family
- * @protected: True if family is protected by access
- * @regs: family specific common registers
- */
-struct mofld_family {
- unsigned int barno;
- unsigned int pin_base;
- size_t npins;
- bool protected;
- void __iomem *regs;
-};
-
-#define MOFLD_FAMILY(b, s, e) \
- { \
- .barno = (b), \
- .pin_base = (s), \
- .npins = (e) - (s) + 1, \
- }
+#include "pinctrl-tangier.h"
static const struct pinctrl_pin_desc mofld_pins[] = {
/* ULPI (13 pins) */
@@ -347,561 +286,39 @@ static const struct pinctrl_pin_desc mofld_pins[] = {
PINCTRL_PIN(250, "JTAG_TRST"),
};
-static const struct mofld_family mofld_families[] = {
- MOFLD_FAMILY(0, 0, 12),
- MOFLD_FAMILY(1, 13, 24),
- MOFLD_FAMILY(2, 25, 44),
- MOFLD_FAMILY(3, 45, 52),
- MOFLD_FAMILY(4, 53, 66),
- MOFLD_FAMILY(5, 67, 88),
- MOFLD_FAMILY(6, 89, 108),
- MOFLD_FAMILY(7, 109, 131),
- MOFLD_FAMILY(8, 132, 151),
- MOFLD_FAMILY(9, 152, 166),
- MOFLD_FAMILY(10, 167, 180),
- MOFLD_FAMILY(11, 181, 195),
- MOFLD_FAMILY(12, 196, 215),
- MOFLD_FAMILY(13, 216, 228),
- MOFLD_FAMILY(14, 229, 250),
+static const struct tng_family mofld_families[] = {
+ TNG_FAMILY(0, 0, 12),
+ TNG_FAMILY(1, 13, 24),
+ TNG_FAMILY(2, 25, 44),
+ TNG_FAMILY(3, 45, 52),
+ TNG_FAMILY(4, 53, 66),
+ TNG_FAMILY(5, 67, 88),
+ TNG_FAMILY(6, 89, 108),
+ TNG_FAMILY(7, 109, 131),
+ TNG_FAMILY(8, 132, 151),
+ TNG_FAMILY(9, 152, 166),
+ TNG_FAMILY(10, 167, 180),
+ TNG_FAMILY(11, 181, 195),
+ TNG_FAMILY(12, 196, 215),
+ TNG_FAMILY(13, 216, 228),
+ TNG_FAMILY(14, 229, 250),
};
-/**
- * struct mofld_pinctrl - Intel Merrifield pinctrl private structure
- * @dev: Pointer to the device structure
- * @lock: Lock to serialize register access
- * @pctldesc: Pin controller description
- * @pctldev: Pointer to the pin controller device
- * @families: Array of families this pinctrl handles
- * @nfamilies: Number of families in the array
- * @functions: Array of functions
- * @nfunctions: Number of functions in the array
- * @groups: Array of pin groups
- * @ngroups: Number of groups in the array
- * @pins: Array of pins this pinctrl controls
- * @npins: Number of pins in the array
- */
-struct mofld_pinctrl {
- struct device *dev;
- raw_spinlock_t lock;
- struct pinctrl_desc pctldesc;
- struct pinctrl_dev *pctldev;
-
- /* Pin controller configuration */
- const struct mofld_family *families;
- size_t nfamilies;
- const struct intel_function *functions;
- size_t nfunctions;
- const struct intel_pingroup *groups;
- size_t ngroups;
- const struct pinctrl_pin_desc *pins;
- size_t npins;
-};
-
-#define pin_to_bufno(f, p) ((p) - (f)->pin_base)
-
-static const struct mofld_family *mofld_get_family(struct mofld_pinctrl *mp, unsigned int pin)
-{
- const struct mofld_family *family;
- unsigned int i;
-
- for (i = 0; i < mp->nfamilies; i++) {
- family = &mp->families[i];
- if (pin >= family->pin_base &&
- pin < family->pin_base + family->npins)
- return family;
- }
-
- dev_warn(mp->dev, "failed to find family for pin %u\n", pin);
- return NULL;
-}
-
-static bool mofld_buf_available(struct mofld_pinctrl *mp, unsigned int pin)
-{
- const struct mofld_family *family;
-
- family = mofld_get_family(mp, pin);
- if (!family)
- return false;
-
- return !family->protected;
-}
-
-static void __iomem *mofld_get_bufcfg(struct mofld_pinctrl *mp, unsigned int pin)
-{
- const struct mofld_family *family;
- unsigned int bufno;
-
- family = mofld_get_family(mp, pin);
- if (!family)
- return NULL;
-
- bufno = pin_to_bufno(family, pin);
- return family->regs + BUFCFG_OFFSET + bufno * 4;
-}
-
-static int mofld_read_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 *value)
-{
- void __iomem *bufcfg;
-
- if (!mofld_buf_available(mp, pin))
- return -EBUSY;
-
- bufcfg = mofld_get_bufcfg(mp, pin);
- *value = readl(bufcfg);
-
- return 0;
-}
-
-static void mofld_update_bufcfg(struct mofld_pinctrl *mp, unsigned int pin, u32 bits, u32 mask)
-{
- void __iomem *bufcfg;
- u32 value;
-
- bufcfg = mofld_get_bufcfg(mp, pin);
- value = readl(bufcfg);
-
- value &= ~mask;
- value |= bits & mask;
-
- writel(value, bufcfg);
-}
-
-static int mofld_get_groups_count(struct pinctrl_dev *pctldev)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->ngroups;
-}
-
-static const char *mofld_get_group_name(struct pinctrl_dev *pctldev, unsigned int group)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->groups[group].grp.name;
-}
-
-static int mofld_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
- const unsigned int **pins, unsigned int *npins)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- *pins = mp->groups[group].grp.pins;
- *npins = mp->groups[group].grp.npins;
- return 0;
-}
-
-static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
- unsigned int pin)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- u32 value, mode;
- int ret;
-
- ret = mofld_read_bufcfg(mp, pin, &value);
- if (ret) {
- seq_puts(s, "not available");
- return;
- }
-
- mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
- if (mode == BUFCFG_PINMODE_GPIO)
- seq_puts(s, "GPIO ");
- else
- seq_printf(s, "mode %d ", mode);
-
- seq_printf(s, "0x%08x", value);
-}
-
-static const struct pinctrl_ops mofld_pinctrl_ops = {
- .get_groups_count = mofld_get_groups_count,
- .get_group_name = mofld_get_group_name,
- .get_group_pins = mofld_get_group_pins,
- .pin_dbg_show = mofld_pin_dbg_show,
-};
-
-static int mofld_get_functions_count(struct pinctrl_dev *pctldev)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->nfunctions;
-}
-
-static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned int function)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- return mp->functions[function].func.name;
-}
-
-static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
- const char * const **groups, unsigned int * const ngroups)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = mp->functions[function].func.groups;
- *ngroups = mp->functions[function].func.ngroups;
- return 0;
-}
-
-static int mofld_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
- unsigned int group)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- const struct intel_pingroup *grp = &mp->groups[group];
- u32 bits = grp->mode << BUFCFG_PINMODE_SHIFT;
- u32 mask = BUFCFG_PINMODE_MASK;
- unsigned long flags;
- unsigned int i;
-
- /*
- * All pins in the groups needs to be accessible and writable
- * before we can enable the mux for this group.
- */
- for (i = 0; i < grp->grp.npins; i++) {
- if (!mofld_buf_available(mp, grp->grp.pins[i]))
- return -EBUSY;
- }
-
- /* Now enable the mux setting for each pin in the group */
- raw_spin_lock_irqsave(&mp->lock, flags);
- for (i = 0; i < grp->grp.npins; i++)
- mofld_update_bufcfg(mp, grp->grp.pins[i], bits, mask);
- raw_spin_unlock_irqrestore(&mp->lock, flags);
-
- return 0;
-}
-
-static int mofld_gpio_request_enable(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range,
- unsigned int pin)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- u32 bits = BUFCFG_PINMODE_GPIO << BUFCFG_PINMODE_SHIFT;
- u32 mask = BUFCFG_PINMODE_MASK;
- unsigned long flags;
-
- if (!mofld_buf_available(mp, pin))
- return -EBUSY;
-
- raw_spin_lock_irqsave(&mp->lock, flags);
- mofld_update_bufcfg(mp, pin, bits, mask);
- raw_spin_unlock_irqrestore(&mp->lock, flags);
-
- return 0;
-}
-
-static const struct pinmux_ops mofld_pinmux_ops = {
- .get_functions_count = mofld_get_functions_count,
- .get_function_name = mofld_get_function_name,
- .get_function_groups = mofld_get_function_groups,
- .set_mux = mofld_pinmux_set_mux,
- .gpio_request_enable = mofld_gpio_request_enable,
-};
-
-static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *config)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- u32 value, term;
- u16 arg = 0;
- int ret;
-
- ret = mofld_read_bufcfg(mp, pin, &value);
- if (ret)
- return -ENOTSUPP;
-
- term = (value & BUFCFG_PUPD_VAL_MASK) >> BUFCFG_PUPD_VAL_SHIFT;
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- if (value & BUFCFG_Px_EN_MASK)
- return -EINVAL;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PU_EN)
- return -EINVAL;
-
- switch (term) {
- case BUFCFG_PUPD_VAL_910:
- arg = 910;
- break;
- case BUFCFG_PUPD_VAL_2K:
- arg = 2000;
- break;
- case BUFCFG_PUPD_VAL_20K:
- arg = 20000;
- break;
- case BUFCFG_PUPD_VAL_50K:
- arg = 50000;
- break;
- }
-
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if ((value & BUFCFG_Px_EN_MASK) != BUFCFG_PD_EN)
- return -EINVAL;
-
- switch (term) {
- case BUFCFG_PUPD_VAL_910:
- arg = 910;
- break;
- case BUFCFG_PUPD_VAL_2K:
- arg = 2000;
- break;
- case BUFCFG_PUPD_VAL_20K:
- arg = 20000;
- break;
- case BUFCFG_PUPD_VAL_50K:
- arg = 50000;
- break;
- }
-
- break;
-
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- if (value & BUFCFG_OD_EN)
- return -EINVAL;
- break;
-
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- if (!(value & BUFCFG_OD_EN))
- return -EINVAL;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (!(value & BUFCFG_SLEWSEL))
- arg = 0;
- else
- arg = 1;
- break;
-
- default:
- return -ENOTSUPP;
- }
-
- *config = pinconf_to_config_packed(param, arg);
- return 0;
-}
-
-static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin,
- unsigned long config)
-{
- unsigned int param = pinconf_to_config_param(config);
- unsigned int arg = pinconf_to_config_argument(config);
- u32 bits = 0, mask = 0;
- unsigned long flags;
-
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
- bits |= BUFCFG_PU_EN;
-
- switch (arg) {
- case 50000:
- bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 20000:
- bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 2000:
- bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- default:
- return -EINVAL;
- }
-
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- mask |= BUFCFG_Px_EN_MASK | BUFCFG_PUPD_VAL_MASK;
- bits |= BUFCFG_PD_EN;
-
- switch (arg) {
- case 50000:
- bits |= BUFCFG_PUPD_VAL_50K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 20000:
- bits |= BUFCFG_PUPD_VAL_20K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- case 2000:
- bits |= BUFCFG_PUPD_VAL_2K << BUFCFG_PUPD_VAL_SHIFT;
- break;
- default:
- return -EINVAL;
- }
-
- break;
-
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- mask |= BUFCFG_OD_EN;
- bits &= ~BUFCFG_OD_EN;
- break;
-
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- mask |= BUFCFG_OD_EN;
- bits |= BUFCFG_OD_EN;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- mask |= BUFCFG_SLEWSEL;
- if (arg)
- bits |= BUFCFG_SLEWSEL;
- break;
- }
-
- raw_spin_lock_irqsave(&mp->lock, flags);
- mofld_update_bufcfg(mp, pin, bits, mask);
- raw_spin_unlock_irqrestore(&mp->lock, flags);
-
- return 0;
-}
-
-static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
- unsigned long *configs, unsigned int nconfigs)
-{
- struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
- unsigned int i;
- int ret;
-
- if (!mofld_buf_available(mp, pin))
- return -ENOTSUPP;
-
- for (i = 0; i < nconfigs; i++) {
- switch (pinconf_to_config_param(configs[i])) {
- case PIN_CONFIG_BIAS_DISABLE:
- case PIN_CONFIG_BIAS_PULL_UP:
- case PIN_CONFIG_BIAS_PULL_DOWN:
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- case PIN_CONFIG_SLEW_RATE:
- ret = mofld_config_set_pin(mp, pin, configs[i]);
- if (ret)
- return ret;
- break;
-
- default:
- return -ENOTSUPP;
- }
- }
-
- return 0;
-}
-
-static int mofld_config_group_get(struct pinctrl_dev *pctldev, unsigned int group,
- unsigned long *config)
-{
- const unsigned int *pins;
- unsigned int npins;
- int ret;
-
- ret = mofld_get_group_pins(pctldev, group, &pins, &npins);
- if (ret)
- return ret;
-
- ret = mofld_config_get(pctldev, pins[0], config);
- if (ret)
- return ret;
-
- return 0;
-}
-
-static int mofld_config_group_set(struct pinctrl_dev *pctldev, unsigned int group,
- unsigned long *configs, unsigned int num_configs)
-{
- const unsigned int *pins;
- unsigned int npins;
- int i, ret;
-
- ret = mofld_get_group_pins(pctldev, group, &pins, &npins);
- if (ret)
- return ret;
-
- for (i = 0; i < npins; i++) {
- ret = mofld_config_set(pctldev, pins[i], configs, num_configs);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-static const struct pinconf_ops mofld_pinconf_ops = {
- .is_generic = true,
- .pin_config_get = mofld_config_get,
- .pin_config_set = mofld_config_set,
- .pin_config_group_get = mofld_config_group_get,
- .pin_config_group_set = mofld_config_group_set,
+static const struct tng_pinctrl mofld_soc_data = {
+ .pins = mofld_pins,
+ .npins = ARRAY_SIZE(mofld_pins),
+ .families = mofld_families,
+ .nfamilies = ARRAY_SIZE(mofld_families),
};
-static const struct pinctrl_desc mofld_pinctrl_desc = {
- .pctlops = &mofld_pinctrl_ops,
- .pmxops = &mofld_pinmux_ops,
- .confops = &mofld_pinconf_ops,
- .owner = THIS_MODULE,
-};
-
-static int mofld_pinctrl_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct mofld_family *families;
- struct mofld_pinctrl *mp;
- void __iomem *regs;
- size_t nfamilies;
- unsigned int i;
-
- mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
- if (!mp)
- return -ENOMEM;
-
- mp->dev = dev;
- raw_spin_lock_init(&mp->lock);
-
- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
- return PTR_ERR(regs);
-
- nfamilies = ARRAY_SIZE(mofld_families),
- families = devm_kmemdup(dev, mofld_families, sizeof(mofld_families), GFP_KERNEL);
- if (!families)
- return -ENOMEM;
-
- /* Splice memory resource by chunk per family */
- for (i = 0; i < nfamilies; i++) {
- struct mofld_family *family = &families[i];
-
- family->regs = regs + family->barno * MOFLD_FAMILY_LEN;
- }
-
- mp->families = families;
- mp->nfamilies = nfamilies;
- mp->pctldesc = mofld_pinctrl_desc;
- mp->pctldesc.name = dev_name(dev);
- mp->pctldesc.pins = mofld_pins;
- mp->pctldesc.npins = ARRAY_SIZE(mofld_pins);
-
- mp->pctldev = devm_pinctrl_register(dev, &mp->pctldesc, mp);
- if (IS_ERR(mp->pctldev))
- return PTR_ERR(mp->pctldev);
-
- platform_set_drvdata(pdev, mp);
- return 0;
-}
-
static const struct acpi_device_id mofld_acpi_table[] = {
- { "INTC1003" },
+ { "INTC1003", (kernel_ulong_t)&mofld_soc_data },
{ }
};
MODULE_DEVICE_TABLE(acpi, mofld_acpi_table);
static struct platform_driver mofld_pinctrl_driver = {
- .probe = mofld_pinctrl_probe,
+ .probe = devm_tng_pinctrl_probe,
.driver = {
.name = "pinctrl-moorefield",
.acpi_match_table = mofld_acpi_table,
@@ -924,3 +341,4 @@ MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
MODULE_DESCRIPTION("Intel Moorefield SoC pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:pinctrl-moorefield");
+MODULE_IMPORT_NS(PINCTRL_TANGIER);
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver
2023-08-14 5:40 [PATCH v1 0/3] Introduce Intel Tangier pinctrl driver Raag Jadav
` (2 preceding siblings ...)
2023-08-14 5:40 ` [PATCH v1 3/3] pinctrl: moorefield: " Raag Jadav
@ 2023-08-15 13:01 ` Andy Shevchenko
3 siblings, 0 replies; 5+ messages in thread
From: Andy Shevchenko @ 2023-08-15 13:01 UTC (permalink / raw)
To: Raag Jadav
Cc: linus.walleij, mika.westerberg, linux-gpio, linux-kernel,
mallikarjunappa.sangannavar, pandith.n
On Mon, Aug 14, 2023 at 11:10:30AM +0530, Raag Jadav wrote:
> Merrifield and Moorefield pinctrl driver implementations are similar
> in terms of how they access the hardware. We can consolidate their
> pinctrl functionalities into a common library driver.
>
> This patch set introduces:
>
> 1. Intel Tangier driver that supports the common pinctrl functionalities
> for Merrifield and Moorefield platforms.
>
> 2. Intel Tangier adaptation for Merrifield pinctrl driver.
>
> 3. Intel Tangier adaptation for Moorefield pinctrl driver.
>
> Tested on Intel Edison platform.
> No deviation observed in the contents of below entries before and after
> this patchset.
>
> - /proc/interrupts
> - /sys/kernel/debug/gpio
> - /sys/kernel/debug/pinctrl/*/pins
Pushed to my review and testing queue, thanks!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 5+ messages in thread