From: Mark Brown <broonie@kernel.org>
To: Witold Sadowski <wsadowski@marvell.com>
Cc: linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, robh@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
pthombar@cadence.com
Subject: Re: [PATCH v8 2/4] spi: cadence: Add Marvell xSPI IP overlay changes
Date: Mon, 10 Jun 2024 17:03:41 +0100 [thread overview]
Message-ID: <Zmcj3fZ4DF8r_qf0@finisterre.sirena.org.uk> (raw)
In-Reply-To: <20240607151831.3858304-3-wsadowski@marvell.com>
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On Fri, Jun 07, 2024 at 08:18:29AM -0700, Witold Sadowski wrote:
> This commit adds support for the basic v2 Marvell overlay block. Key
> features included are:
> - Clock configuration
> - PHY configuration
> - Interrupt configuration (enabling)
This feels like it could usefully be split up so these three bits are
separate, and there appear to be other changes buried in here as well.
I can't tell what changes either the PHY or interrupt configuration
might be referencing.
> @@ -295,6 +450,10 @@ static void cdns_xspi_set_interrupts(struct cdns_xspi_dev *cdns_xspi,
> bool enabled)
> {
> u32 intr_enable;
> + u32 irq_status;
> +
> + irq_status = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
> + writel(irq_status, cdns_xspi->iobase + CDNS_XSPI_INTR_STATUS_REG);
>
> intr_enable = readl(cdns_xspi->iobase + CDNS_XSPI_INTR_ENABLE_REG);
> if (enabled)
This seems like a separate change which applies to everything, not just
Marvell versions of the IP, and should be split out and explained.
> @@ -319,6 +478,9 @@ static int cdns_xspi_controller_init(struct cdns_xspi_dev *cdns_xspi)
> return -EIO;
> }
>
> + writel(FIELD_PREP(CDNS_XSPI_CTRL_WORK_MODE, CDNS_XSPI_WORK_MODE_STIG),
> + cdns_xspi->iobase + CDNS_XSPI_CTRL_CONFIG_REG);
> +
This wasn't clearly mentioned in the changelog and is again being done
unconditionally for all instances of the IP, probably best to split out
and explain.
> +static void mrvl_ioreadq(void __iomem *addr, void *buf, int len)
> +{
> + int i = 0;
> + int rcount = len / 8;
> + int rcount_nf = len % 8;
> + uint64_t tmp;
> + uint64_t *buf64 = (uint64_t *)buf;
Any need to cast away from void * indicates a problem.
> @@ -337,13 +563,11 @@ static void cdns_xspi_sdma_handle(struct cdns_xspi_dev *cdns_xspi)
>
> switch (sdma_dir) {
> case CDNS_XSPI_SDMA_DIR_READ:
> - ioread8_rep(cdns_xspi->sdmabase,
> - cdns_xspi->in_buffer, sdma_size);
> + cdns_xspi_sdma_memread(cdns_xspi, sdma_size);
> break;
It's feeling like it might make sense to have an ops structure rather
than sprinkling checks for the Marvell overlay everywhere.
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next prev parent reply other threads:[~2024-06-10 16:03 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-07 15:18 [PATCH v8 0/4] Marvell HW overlay support for Cadence xSPI Witold Sadowski
2024-06-07 15:18 ` [PATCH v8 1/4] spi: dt-bindings: cadence: Add Marvell overlay bindings documentation for Cadence XSPI Witold Sadowski
2024-06-07 15:18 ` [PATCH v8 2/4] spi: cadence: Add Marvell xSPI IP overlay changes Witold Sadowski
2024-06-10 16:03 ` Mark Brown [this message]
2024-06-11 21:51 ` [EXTERNAL] " Witold Sadowski
2024-06-12 10:31 ` Mark Brown
2024-06-07 15:18 ` [PATCH v8 3/4] spi: cadence: Allow to read basic xSPI configuration from ACPI Witold Sadowski
2024-06-10 16:08 ` Mark Brown
2024-06-11 21:57 ` [EXTERNAL] " Witold Sadowski
2024-06-12 10:35 ` Mark Brown
2024-06-07 15:18 ` [PATCH v8 4/4] spi: cadence: Add MRVL overlay xfer operation support Witold Sadowski
2024-06-10 16:19 ` Mark Brown
2024-06-11 22:02 ` [EXTERNAL] " Witold Sadowski
2024-06-12 10:37 ` Mark Brown
2024-06-18 12:59 ` Witold Sadowski
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