[PATCH 0/2] Add device-tree support for CPSW5G on J7200 SoC

[PATCH 0/2] Add device-tree support for CPSW5G on J7200 SoC

[Siddharth Vadapalli]

Hello,

This series adds the device-tree nodes for CPSW5G instance of CPSW
Ethernet Switch on TI's J7200 SoC. Additionally, an overlay file is also
added to enable CPSW5G nodes in QSGMII mode with the Add-On J7 QUAD Port
Ethernet expansion QSGMII daughtercard.

Siddharth Vadapalli (2):
  arm64: dts: ti: j7200-main: Add CPSW5G nodes
  arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII
    mode

 arch/arm64/boot/dts/ti/Makefile               |   2 +
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     |  83 +++++++++++++++
 .../dts/ti/k3-j7200-quad-port-eth-exp.dtso    | 100 ++++++++++++++++++
 3 files changed, 185 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-quad-port-eth-exp.dtso

-- 
2.25.1

[PATCH 1/2] arm64: dts: ti: j7200-main: Add CPSW5G nodes

[Siddharth Vadapalli]

TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external
ports and 1 host port, referred to as CPSW5G.

Add device-tree nodes for CPSW5G and disable it by default. Device-tree
overlays will be used to enable it.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 83 +++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 138381f43ce4..e9d42ae4ed09 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -39,6 +39,13 @@ serdes_ln_ctrl: mux-controller@4080 {
 					<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
 		};
 
+		cpsw0_phy_gmii_sel: phy@4044 {
+			compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
+			ti,qsgmii-main-ports = <1>;
+			reg = <0x4044 0x10>;
+			#phy-cells = <1>;
+		};
+
 		usb_serdes_mux: mux-controller@4000 {
 			compatible = "mmio-mux";
 			#mux-control-cells = <1>;
@@ -304,6 +311,82 @@ cpts@310d0000 {
 		};
 	};
 
+	cpsw0: ethernet@c000000 {
+		compatible = "ti,j7200-cpswxg-nuss";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		reg = <0x00 0xc000000 0x00 0x200000>;
+		reg-names = "cpsw_nuss";
+		ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+		clocks = <&k3_clks 19 33>;
+		clock-names = "fck";
+		power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+		dmas = <&main_udmap 0xca00>,
+		       <&main_udmap 0xca01>,
+		       <&main_udmap 0xca02>,
+		       <&main_udmap 0xca03>,
+		       <&main_udmap 0xca04>,
+		       <&main_udmap 0xca05>,
+		       <&main_udmap 0xca06>,
+		       <&main_udmap 0xca07>,
+		       <&main_udmap 0x4a00>;
+		dma-names = "tx0", "tx1", "tx2", "tx3",
+			    "tx4", "tx5", "tx6", "tx7",
+			    "rx";
+
+		status = "disabled";
+
+		ethernet-ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			cpsw0_port1: port@1 {
+				reg = <1>;
+				ti,mac-only;
+				label = "port1";
+			};
+
+			cpsw0_port2: port@2 {
+				reg = <2>;
+				ti,mac-only;
+				label = "port2";
+			};
+
+			cpsw0_port3: port@3 {
+				reg = <3>;
+				ti,mac-only;
+				label = "port3";
+			};
+
+			cpsw0_port4: port@4 {
+				reg = <4>;
+				ti,mac-only;
+				label = "port4";
+			};
+		};
+
+		cpsw5g_mdio: mdio@f00 {
+			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+			reg = <0x00 0xf00 0x00 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&k3_clks 19 33>;
+			clock-names = "fck";
+			bus_freq = <1000000>;
+		};
+
+		cpts@3d000 {
+			compatible = "ti,j721e-cpts";
+			reg = <0x00 0x3d000 0x00 0x400>;
+			clocks = <&k3_clks 19 16>;
+			clock-names = "cpts";
+			interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "cpts";
+			ti,cpts-ext-ts-inputs = <4>;
+			ti,cpts-periodic-outputs = <2>;
+		};
+	};
+
 	main_pmx0: pinctrl@11c000 {
 		compatible = "pinctrl-single";
 		/* Proxy 0 addressing */
-- 
2.25.1

[PATCH 2/2] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode

[Siddharth Vadapalli]

The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports
QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode.

Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.

Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses
directly from U-Boot.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/Makefile               |   2 +
 .../dts/ti/k3-j7200-quad-port-eth-exp.dtso    | 100 ++++++++++++++++++
 2 files changed, 102 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-quad-port-eth-exp.dtso

diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 167bcd9b09b7..04e95377a72a 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -45,7 +45,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
 
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
+DTC_FLAGS_k3-j7200-common-proc-board += -@
 DTC_FLAGS_k3-j721e-common-proc-board += -@
 
 # Device-tree overlays
+dtb-$(CONFIG_ARCH_K3) += k3-j7200-quad-port-eth-exp.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j721e-quad-port-eth-exp.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-quad-port-eth-exp.dtso
new file mode 100644
index 000000000000..b84f185c0a31
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-quad-port-eth-exp.dtso
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J7200 board.
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+/ {
+	fragment@101 {
+		target-path = "/";
+		__overlay__ {
+			aliases {
+				ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+				ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+				ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
+				ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
+			};
+		};
+	};
+};
+
+&cpsw0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mdio0_pins_default>;
+};
+
+&cpsw0_port1 {
+	phy-handle = <&cpsw5g_phy0>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+	phy-handle = <&cpsw5g_phy1>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 2>;
+};
+
+&cpsw0_port3 {
+	phy-handle = <&cpsw5g_phy2>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port4 {
+	phy-handle = <&cpsw5g_phy3>;
+	phy-mode = "qsgmii";
+	mac-address = [00 00 00 00 00 00];
+	phys = <&cpsw0_phy_gmii_sel 4>;
+};
+
+&cpsw5g_mdio {
+	reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+	reset-post-delay-us = <120000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	cpsw5g_phy0: ethernet-phy@16 {
+		reg = <16>;
+	};
+	cpsw5g_phy1: ethernet-phy@17 {
+		reg = <17>;
+	};
+	cpsw5g_phy2: ethernet-phy@18 {
+		reg = <18>;
+	};
+	cpsw5g_phy3: ethernet-phy@19 {
+		reg = <19>;
+	};
+};
+
+&exp2 {
+	qsgmii-line-hog {
+		gpio-hog;
+		gpios = <16 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "qsgmii-pwrdn-line";
+	};
+};
+
+&main_pmx0 {
+	mdio0_pins_default: mdio0-pins-default {
+		pinctrl-single,pins = <
+			J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
+			J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
+		>;
+	};
+};
-- 
2.25.1

Re: [PATCH 0/2] Add device-tree support for CPSW5G on J7200 SoC

[Siddharth Vadapalli]

Hello,

This series depends on the series at:
https://lore.kernel.org/r/20230310103504.731845-1-s-vadapalli@ti.com
and will cause merge conflict if merged before it.

Regards,
Siddharth.

On 10/03/23 15:44, Siddharth Vadapalli wrote:
> Hello,
> 
> This series adds the device-tree nodes for CPSW5G instance of CPSW
> Ethernet Switch on TI's J7200 SoC. Additionally, an overlay file is also
> added to enable CPSW5G nodes in QSGMII mode with the Add-On J7 QUAD Port
> Ethernet expansion QSGMII daughtercard.
> 
> Siddharth Vadapalli (2):
>   arm64: dts: ti: j7200-main: Add CPSW5G nodes
>   arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII
>     mode
> 
>  arch/arm64/boot/dts/ti/Makefile               |   2 +
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi     |  83 +++++++++++++++
>  .../dts/ti/k3-j7200-quad-port-eth-exp.dtso    | 100 ++++++++++++++++++
>  3 files changed, 185 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-quad-port-eth-exp.dtso
>