* [PATCH v2 1/2] drm/imagination: Unify repeated register defines
2026-08-10 8:35 [PATCH v2 0/2] Unify repeated register definitions and move FWCORE macros Alexandru Dadu
@ 2026-08-10 8:35 ` Alexandru Dadu
2026-08-10 8:35 ` [PATCH v2 2/2] drm/imagination: Move FWCORE_* macros to " Alexandru Dadu
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Alexandru Dadu @ 2026-08-10 8:35 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-kernel, Alexandru Dadu, Matt Coster
From: Matt Coster <matt.coster@imgtec.com>
Some register definitions are annotated as "Register group: X, with N
repeats". The only difference between all the N copies of those definitions
is the register addresses which can be unified into a BASE/OFFSET pair.
Typical usage patterns of these repeated registers do not involve
hardcoding individual instances, so using any specific defines is
semantically incorrect.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 27 +-
drivers/gpu/drm/imagination/pvr_fw_startstop.c | 24 +-
drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 918 +++---------------------
drivers/gpu/drm/imagination/pvr_rogue_defs.h | 23 +-
drivers/gpu/drm/imagination/pvr_rogue_riscv.h | 2 -
5 files changed, 157 insertions(+), 837 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index fc13d483be9a..d2bd263aa25f 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -23,27 +23,32 @@ static int
pvr_riscv_wrapper_init(struct pvr_device *pvr_dev)
{
const u64 common_opts =
- ((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT)
- << ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT) |
+ ((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT)
+ << ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_SHIFT) |
((u64)MMU_CONTEXT_MAPPING_FWPRIV
- << FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT);
+ << FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_SHIFT);
u64 code_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj);
u64 data_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
/* This condition allows us to OR the addresses into the register directly. */
- static_assert(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT ==
- ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT);
+ static_assert(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_SHIFT ==
+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_ALIGNSHIFT);
- WARN_ON(code_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK);
- WARN_ON(data_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK);
+ WARN_ON(code_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_CLRMSK);
+ WARN_ON(data_addr & ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_CLRMSK);
- pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_CODE),
- code_addr | common_opts | ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN);
+ pvr_cr_write64(pvr_dev,
+ PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG,
+ ROGUE_RISCV_REGION_BOOTLDR_CODE),
+ code_addr | common_opts |
+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN);
- pvr_cr_write64(pvr_dev, ROGUE_RISCVFW_REGION_REMAP_CR(BOOTLDR_DATA),
+ pvr_cr_write64(pvr_dev,
+ PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG,
+ ROGUE_RISCV_REGION_BOOTLDR_DATA),
data_addr | common_opts |
- ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN);
+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_EN);
/* Garten IDLE bit controlled by RISC-V. */
pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG,
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index e24ed6fc4362..98ca2692239d 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -43,19 +43,25 @@ rogue_bif_init(struct pvr_device *pvr_dev)
pc_dma_addr = pvr_vm_get_page_table_root_addr(pvr_dev->kernel_vm_ctx);
/* Write the kernel catalogue base. */
- pc_addr = ((((u64)pc_dma_addr >> ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT)
- << ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT) &
- ~ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK);
+ pc_addr = ((((u64)pc_dma_addr >> ROGUE_CR_BIF_CAT_BASEx_ADDR_ALIGNSHIFT)
+ << ROGUE_CR_BIF_CAT_BASEx_ADDR_SHIFT) &
+ ~ROGUE_CR_BIF_CAT_BASEx_ADDR_CLRMSK);
- pvr_cr_write64(pvr_dev, BIF_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV),
+ pvr_cr_write64(pvr_dev,
+ PVR_CR_REPEAT_X(ROGUE_CR_BIF_CAT_BASE,
+ MMU_CONTEXT_MAPPING_FWPRIV),
pc_addr);
if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV) {
- pc_addr = (((u64)pc_dma_addr >> ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT)
- << ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT) &
- ~ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK;
-
- pvr_cr_write64(pvr_dev, FWCORE_MEM_CAT_BASEX(MMU_CONTEXT_MAPPING_FWPRIV), pc_addr);
+ pc_addr = (((u64)pc_dma_addr
+ >> ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_ALIGNSHIFT)
+ << ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_SHIFT) &
+ ~ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_CLRMSK;
+
+ pvr_cr_write64(pvr_dev,
+ PVR_CR_REPEAT_X(ROGUE_CR_FWCORE_MEM_CAT_BASE,
+ MMU_CONTEXT_MAPPING_FWPRIV),
+ pc_addr);
}
}
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
index 790c97f80a2a..5fbb1ffd0eb9 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
@@ -2344,101 +2344,48 @@
#define ROGUE_CR_ISP_STATUS_EOR_EN 0x00000001U
/* Register group: ROGUE_CR_ISP_XTP_RESUME, with 64 repeats */
-#define ROGUE_CR_ISP_XTP_RESUME_REPEATCOUNT 64U
-/* Register ROGUE_CR_ISP_XTP_RESUME0 */
-#define ROGUE_CR_ISP_XTP_RESUME0 0x3A00U
-#define ROGUE_CR_ISP_XTP_RESUME0_MASKFULL 0x00000000003FF3FFULL
-#define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_SHIFT 12U
-#define ROGUE_CR_ISP_XTP_RESUME0_TILE_X_CLRMSK 0xFFC00FFFU
-#define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_SHIFT 0U
-#define ROGUE_CR_ISP_XTP_RESUME0_TILE_Y_CLRMSK 0xFFFFFC00U
+#define ROGUE_CR_ISP_XTP_RESUME_REPEAT_COUNT 64U
+#define ROGUE_CR_ISP_XTP_RESUME_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_ISP_XTP_RESUME_REPEAT_BASE 0x3A00U
+/* Register ROGUE_CR_ISP_XTP_RESUMEx */
+#define ROGUE_CR_ISP_XTP_RESUMEx_MASKFULL 0x00000000003FF3FFULL
+#define ROGUE_CR_ISP_XTP_RESUMEx_TILE_X_SHIFT 12U
+#define ROGUE_CR_ISP_XTP_RESUMEx_TILE_X_CLRMSK 0xFFC00FFFU
+#define ROGUE_CR_ISP_XTP_RESUMEx_TILE_Y_SHIFT 0U
+#define ROGUE_CR_ISP_XTP_RESUMEx_TILE_Y_CLRMSK 0xFFFFFC00U
/* Register group: ROGUE_CR_ISP_XTP_STORE, with 32 repeats */
-#define ROGUE_CR_ISP_XTP_STORE_REPEATCOUNT 32U
-/* Register ROGUE_CR_ISP_XTP_STORE0 */
-#define ROGUE_CR_ISP_XTP_STORE0 0x3C00U
-#define ROGUE_CR_ISP_XTP_STORE0_MASKFULL 0x000000007F3FF3FFULL
-#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_SHIFT 30U
-#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_CLRMSK 0xBFFFFFFFU
-#define ROGUE_CR_ISP_XTP_STORE0_ACTIVE_EN 0x40000000U
-#define ROGUE_CR_ISP_XTP_STORE0_EOR_SHIFT 29U
-#define ROGUE_CR_ISP_XTP_STORE0_EOR_CLRMSK 0xDFFFFFFFU
-#define ROGUE_CR_ISP_XTP_STORE0_EOR_EN 0x20000000U
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_SHIFT 28U
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_CLRMSK 0xEFFFFFFFU
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_LAST_EN 0x10000000U
-#define ROGUE_CR_ISP_XTP_STORE0_MT_SHIFT 24U
-#define ROGUE_CR_ISP_XTP_STORE0_MT_CLRMSK 0xF0FFFFFFU
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_X_SHIFT 12U
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_X_CLRMSK 0xFFC00FFFU
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_SHIFT 0U
-#define ROGUE_CR_ISP_XTP_STORE0_TILE_Y_CLRMSK 0xFFFFFC00U
+#define ROGUE_CR_ISP_XTP_STORE_REPEAT_COUNT 32U
+#define ROGUE_CR_ISP_XTP_STORE_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_ISP_XTP_STORE_REPEAT_BASE 0x3C00U
+/* Register ROGUE_CR_ISP_XTP_STOREx */
+#define ROGUE_CR_ISP_XTP_STOREx_MASKFULL 0x000000007F3FF3FFULL
+#define ROGUE_CR_ISP_XTP_STOREx_ACTIVE_SHIFT 30U
+#define ROGUE_CR_ISP_XTP_STOREx_ACTIVE_CLRMSK 0xBFFFFFFFU
+#define ROGUE_CR_ISP_XTP_STOREx_ACTIVE_EN 0x40000000U
+#define ROGUE_CR_ISP_XTP_STOREx_EOR_SHIFT 29U
+#define ROGUE_CR_ISP_XTP_STOREx_EOR_CLRMSK 0xDFFFFFFFU
+#define ROGUE_CR_ISP_XTP_STOREx_EOR_EN 0x20000000U
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_LAST_SHIFT 28U
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_LAST_CLRMSK 0xEFFFFFFFU
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_LAST_EN 0x10000000U
+#define ROGUE_CR_ISP_XTP_STOREx_MT_SHIFT 24U
+#define ROGUE_CR_ISP_XTP_STOREx_MT_CLRMSK 0xF0FFFFFFU
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_X_SHIFT 12U
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_X_CLRMSK 0xFFC00FFFU
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_Y_SHIFT 0U
+#define ROGUE_CR_ISP_XTP_STOREx_TILE_Y_CLRMSK 0xFFFFFC00U
/* Register group: ROGUE_CR_BIF_CAT_BASE, with 8 repeats */
-#define ROGUE_CR_BIF_CAT_BASE_REPEATCOUNT 8U
-/* Register ROGUE_CR_BIF_CAT_BASE0 */
-#define ROGUE_CR_BIF_CAT_BASE0 0x1200U
-#define ROGUE_CR_BIF_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE0_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE0_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE1 */
-#define ROGUE_CR_BIF_CAT_BASE1 0x1208U
-#define ROGUE_CR_BIF_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE1_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE1_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE2 */
-#define ROGUE_CR_BIF_CAT_BASE2 0x1210U
-#define ROGUE_CR_BIF_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE2_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE2_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE3 */
-#define ROGUE_CR_BIF_CAT_BASE3 0x1218U
-#define ROGUE_CR_BIF_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE3_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE3_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE4 */
-#define ROGUE_CR_BIF_CAT_BASE4 0x1220U
-#define ROGUE_CR_BIF_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE4_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE4_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE5 */
-#define ROGUE_CR_BIF_CAT_BASE5 0x1228U
-#define ROGUE_CR_BIF_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE5_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE5_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE6 */
-#define ROGUE_CR_BIF_CAT_BASE6 0x1230U
-#define ROGUE_CR_BIF_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE6_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE6_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_CAT_BASE7 */
-#define ROGUE_CR_BIF_CAT_BASE7 0x1238U
-#define ROGUE_CR_BIF_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_BIF_CAT_BASE7_ADDR_SHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_CAT_BASE7_ADDR_ALIGNSIZE 4096U
+#define ROGUE_CR_BIF_CAT_BASE_REPEAT_COUNT 8U
+#define ROGUE_CR_BIF_CAT_BASE_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_BIF_CAT_BASE_REPEAT_BASE 0x1200U
+/* Register ROGUE_CR_BIF_CAT_BASEx */
+#define ROGUE_CR_BIF_CAT_BASEx_MASKFULL 0x000000FFFFFFF000ULL
+#define ROGUE_CR_BIF_CAT_BASEx_ADDR_SHIFT 12U
+#define ROGUE_CR_BIF_CAT_BASEx_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
+#define ROGUE_CR_BIF_CAT_BASEx_ADDR_ALIGNSHIFT 12U
+#define ROGUE_CR_BIF_CAT_BASEx_ADDR_ALIGNSIZE 4096U
/* Register ROGUE_CR_BIF_CAT_BASE_INDEX */
#define ROGUE_CR_BIF_CAT_BASE_INDEX 0x1240U
@@ -2715,142 +2662,24 @@
#define ROGUE_CR_BIF_MMU_STATUS_BUSY_EN 0x00000001U
/* Register group: ROGUE_CR_BIF_TILING_CFG, with 8 repeats */
-#define ROGUE_CR_BIF_TILING_CFG_REPEATCOUNT 8U
-/* Register ROGUE_CR_BIF_TILING_CFG0 */
-#define ROGUE_CR_BIF_TILING_CFG0 0x12D8U
-#define ROGUE_CR_BIF_TILING_CFG0_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG0_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG0_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG0_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG0_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG1 */
-#define ROGUE_CR_BIF_TILING_CFG1 0x12E0U
-#define ROGUE_CR_BIF_TILING_CFG1_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG1_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG1_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG1_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG1_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG2 */
-#define ROGUE_CR_BIF_TILING_CFG2 0x12E8U
-#define ROGUE_CR_BIF_TILING_CFG2_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG2_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG2_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG2_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG2_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG3 */
-#define ROGUE_CR_BIF_TILING_CFG3 0x12F0U
-#define ROGUE_CR_BIF_TILING_CFG3_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG3_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG3_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG3_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG3_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG4 */
-#define ROGUE_CR_BIF_TILING_CFG4 0x12F8U
-#define ROGUE_CR_BIF_TILING_CFG4_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG4_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG4_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG4_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG4_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG5 */
-#define ROGUE_CR_BIF_TILING_CFG5 0x1300U
-#define ROGUE_CR_BIF_TILING_CFG5_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG5_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG5_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG5_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG5_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG6 */
-#define ROGUE_CR_BIF_TILING_CFG6 0x1308U
-#define ROGUE_CR_BIF_TILING_CFG6_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG6_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG6_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG6_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG6_MIN_ADDRESS_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_BIF_TILING_CFG7 */
-#define ROGUE_CR_BIF_TILING_CFG7 0x1310U
-#define ROGUE_CR_BIF_TILING_CFG7_MASKFULL 0xFFFFFFFF0FFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_SHIFT 61U
-#define ROGUE_CR_BIF_TILING_CFG7_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_SHIFT 60U
-#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG7_ENABLE_EN 0x1000000000000000ULL
-#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_SHIFT 32U
-#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
-#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG7_MAX_ADDRESS_ALIGNSIZE 4096U
-#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_SHIFT 0U
-#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
-#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSHIFT 12U
-#define ROGUE_CR_BIF_TILING_CFG7_MIN_ADDRESS_ALIGNSIZE 4096U
+#define ROGUE_CR_BIF_TILING_CFG_REPEAT_COUNT 8U
+#define ROGUE_CR_BIF_TILING_CFG_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_BIF_TILING_CFG_REPEAT_BASE 0x12D8U
+/* Register ROGUE_CR_BIF_TILING_CFGx */
+#define ROGUE_CR_BIF_TILING_CFGx_MASKFULL 0xFFFFFFFF0FFFFFFFULL
+#define ROGUE_CR_BIF_TILING_CFGx_XSTRIDE_SHIFT 61U
+#define ROGUE_CR_BIF_TILING_CFGx_XSTRIDE_CLRMSK 0x1FFFFFFFFFFFFFFFULL
+#define ROGUE_CR_BIF_TILING_CFGx_ENABLE_SHIFT 60U
+#define ROGUE_CR_BIF_TILING_CFGx_ENABLE_CLRMSK 0xEFFFFFFFFFFFFFFFULL
+#define ROGUE_CR_BIF_TILING_CFGx_ENABLE_EN 0x1000000000000000ULL
+#define ROGUE_CR_BIF_TILING_CFGx_MAX_ADDRESS_SHIFT 32U
+#define ROGUE_CR_BIF_TILING_CFGx_MAX_ADDRESS_CLRMSK 0xF0000000FFFFFFFFULL
+#define ROGUE_CR_BIF_TILING_CFGx_MAX_ADDRESS_ALIGNSHIFT 12U
+#define ROGUE_CR_BIF_TILING_CFGx_MAX_ADDRESS_ALIGNSIZE 4096U
+#define ROGUE_CR_BIF_TILING_CFGx_MIN_ADDRESS_SHIFT 0U
+#define ROGUE_CR_BIF_TILING_CFGx_MIN_ADDRESS_CLRMSK 0xFFFFFFFFF0000000ULL
+#define ROGUE_CR_BIF_TILING_CFGx_MIN_ADDRESS_ALIGNSHIFT 12U
+#define ROGUE_CR_BIF_TILING_CFGx_MIN_ADDRESS_ALIGNSIZE 4096U
/* Register ROGUE_CR_BIF_READS_EXT_STATUS */
#define ROGUE_CR_BIF_READS_EXT_STATUS 0x1320U
@@ -2951,102 +2780,13 @@
#define ROGUE_CR_MCU_FENCE_ADDR_ALIGNSIZE 32U
/* Register group: ROGUE_CR_SCRATCH, with 16 repeats */
-#define ROGUE_CR_SCRATCH_REPEATCOUNT 16U
-/* Register ROGUE_CR_SCRATCH0 */
-#define ROGUE_CR_SCRATCH0 0x1A00U
-#define ROGUE_CR_SCRATCH0_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH0_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH0_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH1 */
-#define ROGUE_CR_SCRATCH1 0x1A08U
-#define ROGUE_CR_SCRATCH1_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH1_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH1_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH2 */
-#define ROGUE_CR_SCRATCH2 0x1A10U
-#define ROGUE_CR_SCRATCH2_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH2_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH2_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH3 */
-#define ROGUE_CR_SCRATCH3 0x1A18U
-#define ROGUE_CR_SCRATCH3_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH3_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH3_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH4 */
-#define ROGUE_CR_SCRATCH4 0x1A20U
-#define ROGUE_CR_SCRATCH4_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH4_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH4_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH5 */
-#define ROGUE_CR_SCRATCH5 0x1A28U
-#define ROGUE_CR_SCRATCH5_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH5_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH5_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH6 */
-#define ROGUE_CR_SCRATCH6 0x1A30U
-#define ROGUE_CR_SCRATCH6_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH6_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH6_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH7 */
-#define ROGUE_CR_SCRATCH7 0x1A38U
-#define ROGUE_CR_SCRATCH7_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH7_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH7_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH8 */
-#define ROGUE_CR_SCRATCH8 0x1A40U
-#define ROGUE_CR_SCRATCH8_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH8_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH8_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH9 */
-#define ROGUE_CR_SCRATCH9 0x1A48U
-#define ROGUE_CR_SCRATCH9_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH9_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH9_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH10 */
-#define ROGUE_CR_SCRATCH10 0x1A50U
-#define ROGUE_CR_SCRATCH10_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH10_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH10_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH11 */
-#define ROGUE_CR_SCRATCH11 0x1A58U
-#define ROGUE_CR_SCRATCH11_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH11_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH11_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH12 */
-#define ROGUE_CR_SCRATCH12 0x1A60U
-#define ROGUE_CR_SCRATCH12_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH12_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH12_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH13 */
-#define ROGUE_CR_SCRATCH13 0x1A68U
-#define ROGUE_CR_SCRATCH13_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH13_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH13_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH14 */
-#define ROGUE_CR_SCRATCH14 0x1A70U
-#define ROGUE_CR_SCRATCH14_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH14_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH14_DATA_CLRMSK 0x00000000U
-
-/* Register ROGUE_CR_SCRATCH15 */
-#define ROGUE_CR_SCRATCH15 0x1A78U
-#define ROGUE_CR_SCRATCH15_MASKFULL 0x00000000FFFFFFFFULL
-#define ROGUE_CR_SCRATCH15_DATA_SHIFT 0U
-#define ROGUE_CR_SCRATCH15_DATA_CLRMSK 0x00000000U
+#define ROGUE_CR_SCRATCH_REPEAT_COUNT 16U
+#define ROGUE_CR_SCRATCH_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_SCRATCH_REPEAT_BASE 0x1A00U
+/* Register ROGUE_CR_SCRATCHx */
+#define ROGUE_CR_SCRATCHx_MASKFULL 0x00000000FFFFFFFFULL
+#define ROGUE_CR_SCRATCHx_DATA_SHIFT 0U
+#define ROGUE_CR_SCRATCHx_DATA_CLRMSK 0x00000000U
/* Register group: ROGUE_CR_OS0_SCRATCH, with 2 repeats */
#define ROGUE_CR_OS0_SCRATCH_REPEATCOUNT 2U
@@ -3273,342 +3013,28 @@
#define ROGUE_CR_SPFILTER_SIGNAL_DESCR_MIN_ADDR_ALIGNSIZE 16U
/* Register group: ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG, with 16 repeats */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEATCOUNT 16U
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 0x3000U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1 0x3008U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG1_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2 0x3010U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG2_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3 0x3018U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG3_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4 0x3020U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG4_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5 0x3028U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG5_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6 0x3030U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG6_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7 0x3038U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG7_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8 0x3040U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG8_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9 0x3048U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG9_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10 0x3050U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG10_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11 0x3058U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG11_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12 0x3060U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG12_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13 0x3068U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG13_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14 0x3070U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG14_DEVVADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 */
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15 0x3078U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_MASKFULL 0x7FFFF7FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_SHIFT 62U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_TRUSTED_EN 0x4000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_SHIFT 61U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_LOAD_STORE_EN_EN 0x2000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_SHIFT 60U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_FETCH_EN_EN 0x1000000000000000ULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_SHIFT 44U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_SHIFT 40U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG15_DEVVADDR_ALIGNSIZE 4096U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEAT_COUNT 16U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG_REPEAT_BASE 0x3000U
+/* Register ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx */
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_MASKFULL 0x7FFFF7FFFFFFF000ULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_TRUSTED_SHIFT 62U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_TRUSTED_CLRMSK 0xBFFFFFFFFFFFFFFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_TRUSTED_EN 0x4000000000000000ULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_SHIFT 61U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_CLRMSK 0xDFFFFFFFFFFFFFFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_LOAD_STORE_EN_EN 0x2000000000000000ULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_SHIFT 60U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_CLRMSK 0xEFFFFFFFFFFFFFFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN 0x1000000000000000ULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_SHIFT 44U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT 40U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_SHIFT 12U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_CLRMSK 0xFFFFFF0000000FFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_ALIGNSHIFT 12U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_ALIGNSIZE 4096U
/* Register ROGUE_CR_FWCORE_BOOT */
#define ROGUE_CR_FWCORE_BOOT 0x3090U
@@ -3726,70 +3152,15 @@
#define ROGUE_CR_FWCORE_WRAPPER_FENCE_ID_EN 0x00000001U
/* Register group: ROGUE_CR_FWCORE_MEM_CAT_BASE, with 8 repeats */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEATCOUNT 8U
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE0 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE0 0x30F0U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE0_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE1 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE1 0x30F8U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE1_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE2 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE2 0x3100U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE2_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE3 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE3 0x3108U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE3_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE4 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE4 0x3110U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE4_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE5 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE5 0x3118U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE5_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE6 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE6 0x3120U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE6_ADDR_ALIGNSIZE 4096U
-
-/* Register ROGUE_CR_FWCORE_MEM_CAT_BASE7 */
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE7 0x3128U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_MASKFULL 0x000000FFFFFFF000ULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_SHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSHIFT 12U
-#define ROGUE_CR_FWCORE_MEM_CAT_BASE7_ADDR_ALIGNSIZE 4096U
+#define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEAT_COUNT 8U
+#define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_MEM_CAT_BASE_REPEAT_BASE 0x30F0U
+/* Register ROGUE_CR_FWCORE_MEM_CAT_BASEx */
+#define ROGUE_CR_FWCORE_MEM_CAT_BASEx_MASKFULL 0x000000FFFFFFF000ULL
+#define ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_SHIFT 12U
+#define ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_CLRMSK 0xFFFFFF0000000FFFULL
+#define ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_ALIGNSHIFT 12U
+#define ROGUE_CR_FWCORE_MEM_CAT_BASEx_ADDR_ALIGNSIZE 4096U
/* Register ROGUE_CR_FWCORE_WDT_RESET */
#define ROGUE_CR_FWCORE_WDT_RESET 0x3130U
@@ -3816,22 +3187,11 @@
#define ROGUE_CR_FWCORE_WDT_COUNT_VALUE_CLRMSK 0x00000000U
/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED0, with 4 repeats */
-#define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEATCOUNT 4U
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED00 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED00 0x3400U
-#define ROGUE_CR_FWCORE_DMI_RESERVED00_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED01 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED01 0x3408U
-#define ROGUE_CR_FWCORE_DMI_RESERVED01_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED02 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED02 0x3410U
-#define ROGUE_CR_FWCORE_DMI_RESERVED02_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED03 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED03 0x3418U
-#define ROGUE_CR_FWCORE_DMI_RESERVED03_MASKFULL 0x0000000000000000ULL
+#define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEAT_COUNT 4U
+#define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_DMI_RESERVED0_REPEAT_BASE 0x3400U
+/* Register ROGUE_CR_FWCORE_DMI_RESERVED0x */
+#define ROGUE_CR_FWCORE_DMI_RESERVED0x_MASKFULL 0x0000000000000000ULL
/* Register ROGUE_CR_FWCORE_DMI_DATA0 */
#define ROGUE_CR_FWCORE_DMI_DATA0 0x3420U
@@ -3842,26 +3202,11 @@
#define ROGUE_CR_FWCORE_DMI_DATA1_MASKFULL 0x0000000000000000ULL
/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED1, with 5 repeats */
-#define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEATCOUNT 5U
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED10 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED10 0x3430U
-#define ROGUE_CR_FWCORE_DMI_RESERVED10_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED11 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED11 0x3438U
-#define ROGUE_CR_FWCORE_DMI_RESERVED11_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED12 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED12 0x3440U
-#define ROGUE_CR_FWCORE_DMI_RESERVED12_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED13 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED13 0x3448U
-#define ROGUE_CR_FWCORE_DMI_RESERVED13_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED14 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED14 0x3450U
-#define ROGUE_CR_FWCORE_DMI_RESERVED14_MASKFULL 0x0000000000000000ULL
+#define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEAT_COUNT 5U
+#define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_DMI_RESERVED1_REPEAT_BASE 0x3430U
+/* Register ROGUE_CR_FWCORE_DMI_RESERVED1x */
+#define ROGUE_CR_FWCORE_DMI_RESERVED1x_MASKFULL 0x0000000000000000ULL
/* Register ROGUE_CR_FWCORE_DMI_DMCONTROL */
#define ROGUE_CR_FWCORE_DMI_DMCONTROL 0x3480U
@@ -3872,22 +3217,11 @@
#define ROGUE_CR_FWCORE_DMI_DMSTATUS_MASKFULL 0x0000000000000000ULL
/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED2, with 4 repeats */
-#define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEATCOUNT 4U
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED20 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED20 0x3490U
-#define ROGUE_CR_FWCORE_DMI_RESERVED20_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED21 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED21 0x3498U
-#define ROGUE_CR_FWCORE_DMI_RESERVED21_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED22 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED22 0x34A0U
-#define ROGUE_CR_FWCORE_DMI_RESERVED22_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED23 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED23 0x34A8U
-#define ROGUE_CR_FWCORE_DMI_RESERVED23_MASKFULL 0x0000000000000000ULL
+#define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEAT_COUNT 4U
+#define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_DMI_RESERVED2_REPEAT_BASE 0x3490U
+/* Register ROGUE_CR_FWCORE_DMI_RESERVED2x */
+#define ROGUE_CR_FWCORE_DMI_RESERVED2x_MASKFULL 0x0000000000000000ULL
/* Register ROGUE_CR_FWCORE_DMI_ABSTRACTCS */
#define ROGUE_CR_FWCORE_DMI_ABSTRACTCS 0x34B0U
@@ -3906,32 +3240,18 @@
#define ROGUE_CR_FWCORE_DMI_SBADDRESS0_MASKFULL 0x0000000000000000ULL
/* Register group: ROGUE_CR_FWCORE_DMI_RESERVED3, with 2 repeats */
-#define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEATCOUNT 2U
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED30 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED30 0x34D0U
-#define ROGUE_CR_FWCORE_DMI_RESERVED30_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_RESERVED31 */
-#define ROGUE_CR_FWCORE_DMI_RESERVED31 0x34D8U
-#define ROGUE_CR_FWCORE_DMI_RESERVED31_MASKFULL 0x0000000000000000ULL
+#define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEAT_COUNT 2U
+#define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_DMI_RESERVED3_REPEAT_BASE 0x34D0U
+/* Register ROGUE_CR_FWCORE_DMI_RESERVED3x */
+#define ROGUE_CR_FWCORE_DMI_RESERVED3x_MASKFULL 0x0000000000000000ULL
/* Register group: ROGUE_CR_FWCORE_DMI_SBDATA, with 4 repeats */
-#define ROGUE_CR_FWCORE_DMI_SBDATA_REPEATCOUNT 4U
-/* Register ROGUE_CR_FWCORE_DMI_SBDATA0 */
-#define ROGUE_CR_FWCORE_DMI_SBDATA0 0x35E0U
-#define ROGUE_CR_FWCORE_DMI_SBDATA0_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_SBDATA1 */
-#define ROGUE_CR_FWCORE_DMI_SBDATA1 0x35E8U
-#define ROGUE_CR_FWCORE_DMI_SBDATA1_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_SBDATA2 */
-#define ROGUE_CR_FWCORE_DMI_SBDATA2 0x35F0U
-#define ROGUE_CR_FWCORE_DMI_SBDATA2_MASKFULL 0x0000000000000000ULL
-
-/* Register ROGUE_CR_FWCORE_DMI_SBDATA3 */
-#define ROGUE_CR_FWCORE_DMI_SBDATA3 0x35F8U
-#define ROGUE_CR_FWCORE_DMI_SBDATA3_MASKFULL 0x0000000000000000ULL
+#define ROGUE_CR_FWCORE_DMI_SBDATA_REPEAT_COUNT 4U
+#define ROGUE_CR_FWCORE_DMI_SBDATA_REPEAT_OFFSET 0x0008U
+#define ROGUE_CR_FWCORE_DMI_SBDATA_REPEAT_BASE 0x35E0U
+/* Register ROGUE_CR_FWCORE_DMI_SBDATAx */
+#define ROGUE_CR_FWCORE_DMI_SBDATAx_MASKFULL 0x0000000000000000ULL
/* Register ROGUE_CR_FWCORE_DMI_HALTSUM0 */
#define ROGUE_CR_FWCORE_DMI_HALTSUM0 0x3600U
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_defs.h
index 932b01686008..035e2ea39434 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_defs.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_defs.h
@@ -93,26 +93,17 @@
#define MMU_CONTEXT_MAPPING_FWPRIV (0x0) /* FW code/private data */
#define MMU_CONTEXT_MAPPING_FWIF (0x0) /* Host/FW data */
-/*
- * Utility macros to calculate CAT_BASE register addresses
- */
-#define BIF_CAT_BASEX(n) \
- (ROGUE_CR_BIF_CAT_BASE0 + \
- (n) * (ROGUE_CR_BIF_CAT_BASE1 - ROGUE_CR_BIF_CAT_BASE0))
-
-#define FWCORE_MEM_CAT_BASEX(n) \
- (ROGUE_CR_FWCORE_MEM_CAT_BASE0 + \
- (n) * (ROGUE_CR_FWCORE_MEM_CAT_BASE1 - \
- ROGUE_CR_FWCORE_MEM_CAT_BASE0))
+/* Utility macro for accessing instances of repeated registers */
+#define PVR_CR_REPEAT_X(REG, N) ((REG##_REPEAT_BASE) + (N) * (REG##_REPEAT_OFFSET))
/*
* FWCORE wrapper register defines
*/
-#define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_SHIFT \
- ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_SHIFT
-#define FWCORE_ADDR_REMAP_CONFIG0_MMU_CONTEXT_CLRMSK \
- ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0_CBASE_CLRMSK
-#define FWCORE_ADDR_REMAP_CONFIG0_SIZE_ALIGNSHIFT (12U)
+#define FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_SHIFT \
+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT
+#define FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_CLRMSK \
+ ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_CLRMSK
+#define FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT (12U)
#define ROGUE_MAX_COMPUTE_SHARED_REGISTERS (2 * 1024)
#define ROGUE_MAX_VERTEX_SHARED_REGISTERS 1024
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h b/drivers/gpu/drm/imagination/pvr_rogue_riscv.h
index 9a070e24fa6a..d971729e18a4 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_riscv.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_riscv.h
@@ -35,7 +35,5 @@ enum rogue_riscvfw_region {
};
#define ROGUE_RISCVFW_REGION_BASE(r) ((u32)(ROGUE_RISCV_REGION_##r) << ROGUE_RISCVFW_REGION_SHIFT)
-#define ROGUE_RISCVFW_REGION_REMAP_CR(r) \
- (ROGUE_CR_FWCORE_ADDR_REMAP_CONFIG0 + (u32)(ROGUE_RISCV_REGION_##r) * 8U)
#endif /* PVR_ROGUE_RISCV_H */
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v2 2/2] drm/imagination: Move FWCORE_* macros to register defines
2026-08-10 8:35 [PATCH v2 0/2] Unify repeated register definitions and move FWCORE macros Alexandru Dadu
2026-08-10 8:35 ` [PATCH v2 1/2] drm/imagination: Unify repeated register defines Alexandru Dadu
@ 2026-08-10 8:35 ` Alexandru Dadu
2026-09-14 12:54 ` [PATCH v2 0/2] Unify repeated register definitions and move FWCORE macros Alessio Belle
2026-09-15 15:13 ` Alessio Belle
3 siblings, 0 replies; 5+ messages in thread
From: Alexandru Dadu @ 2026-08-10 8:35 UTC (permalink / raw)
To: Alessio Belle, Luigi Santivetti, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti
Cc: imagination, dri-devel, linux-kernel, Alexandru Dadu, Matt Coster
From: Matt Coster <matt.coster@imgtec.com>
FWCORE_* macros moved to pvr_rogue_cr_defs.h where they should have been
from the beginning.
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
drivers/gpu/drm/imagination/pvr_fw_riscv.c | 5 +++--
drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h | 2 ++
drivers/gpu/drm/imagination/pvr_rogue_defs.h | 9 ---------
3 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/imagination/pvr_fw_riscv.c b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
index d2bd263aa25f..c160ec9e3ff2 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_riscv.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_riscv.c
@@ -23,10 +23,11 @@ static int
pvr_riscv_wrapper_init(struct pvr_device *pvr_dev)
{
const u64 common_opts =
- ((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT)
+ ((u64)(ROGUE_FW_HEAP_RISCV_SIZE
+ >> ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT)
<< ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_SHIFT) |
((u64)MMU_CONTEXT_MAPPING_FWPRIV
- << FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_SHIFT);
+ << ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT);
u64 code_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj);
u64 data_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
index 5fbb1ffd0eb9..45d784f2a82c 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
@@ -3029,6 +3029,8 @@
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN 0x1000000000000000ULL
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_SHIFT 44U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT 12U
+#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSIZE 4096U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT 40U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_SHIFT 12U
diff --git a/drivers/gpu/drm/imagination/pvr_rogue_defs.h b/drivers/gpu/drm/imagination/pvr_rogue_defs.h
index 035e2ea39434..f09ab85e590a 100644
--- a/drivers/gpu/drm/imagination/pvr_rogue_defs.h
+++ b/drivers/gpu/drm/imagination/pvr_rogue_defs.h
@@ -96,15 +96,6 @@
/* Utility macro for accessing instances of repeated registers */
#define PVR_CR_REPEAT_X(REG, N) ((REG##_REPEAT_BASE) + (N) * (REG##_REPEAT_OFFSET))
-/*
- * FWCORE wrapper register defines
- */
-#define FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_SHIFT \
- ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT
-#define FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_CLRMSK \
- ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_CLRMSK
-#define FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT (12U)
-
#define ROGUE_MAX_COMPUTE_SHARED_REGISTERS (2 * 1024)
#define ROGUE_MAX_VERTEX_SHARED_REGISTERS 1024
#define ROGUE_MAX_PIXEL_SHARED_REGISTERS 1024
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread