Re: [PATCH 3/3] clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller

[Taniya Das <quic_tdas@quicinc.com>]

On 12/4/2024 3:35 PM, Krzysztof Kozlowski wrote:
> On 03/12/2024 23:09, Stephen Boyd wrote:
>> Quoting Krzysztof Kozlowski (2024-11-28 07:08:01)
>>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>>> index 2ec9be21ff678e3343cccafa85801aa68805f440..d9ab42c625ddd61f9bf1857522d44d4547e42bf5 100644
>>> --- a/drivers/clk/qcom/Kconfig
>>> +++ b/drivers/clk/qcom/Kconfig
>>> @@ -1022,6 +1022,16 @@ config SM_DISPCC_8550
>>>            Say Y if you want to support display devices and functionality such as
>>>            splash screen.
>>>   
>>> +config SM_DISPCC_8750
>>> +       tristate "SM8750 Display Clock Controller"
>>> +       depends on ARM64 || COMPILE_TEST
>>
>> Please select QCOM_GDSC
> 
> Ack
> 
>>
>>> +       depends on SM_GCC_8750
>>
>> select? Or imply? It's a functional dependency, not a build time one.
> 
> ARM64 is as well functional dependency, ARCH_QCOM present in all other
> drivers as well. It is all the same. The point is to limit the config
> options available to users/distros when they do not need them. In this
> particular case: if user does not select main clock controller (GCC)
> then allowing to choose Display clock controller is pointless.
> 
>>
>>> +       help
>>> diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c
>>> new file mode 100644
>>> index 0000000000000000000000000000000000000000..ff64ff93c4dbdd2aae22b55dd0e404544cc9373e
>>> --- /dev/null
>>> +++ b/drivers/clk/qcom/dispcc-sm8750.c
>>> @@ -0,0 +1,1960 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2023-2024, Linaro Ltd.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>
>> Is this include used?
> 
> Not used, copy pasta from older driver. I'll clean it up.
> 
>>
>>> +#include <linux/clk-provider.h>
>>> +#include <linux/err.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/regmap.h>
>>> +#include <linux/pm_runtime.h>
>>> +
>>> +#include <dt-bindings/clock/qcom,sm8750-dispcc.h>
>>> +
>>> +#include "common.h"
>>> +#include "clk-alpha-pll.h"
>>> +#include "clk-branch.h"
>>> +#include "clk-pll.h"
>>> +#include "clk-rcg.h"
>>> +#include "clk-regmap.h"
>>> +#include "clk-regmap-divider.h"
>>> +#include "clk-regmap-mux.h"
>>> +#include "reset.h"
>>> +#include "gdsc.h"
>> [...]
>>> +};
>>> +
>>> +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
>>> +       .cmd_rcgr = 0x8150,
>>> +       .mnd_width = 0,
>>> +       .hid_width = 5,
>>> +       .parent_map = disp_cc_parent_map_9,
>>> +       .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
>>> +       .clkr.hw.init = &(const struct clk_init_data) {
>>> +               .name = "disp_cc_mdss_mdp_clk_src",
>>> +               .parent_data = disp_cc_parent_data_9,
>>> +               .num_parents = ARRAY_SIZE(disp_cc_parent_data_9),
>>> +               .flags = CLK_SET_RATE_PARENT,
>>> +               .ops = &clk_rcg2_shared_ops, /* TODO: switch to cesta managed clocks */
>>
>> What is cesta?
> 
> Cesta is a new hardware block which receives votes from consumers and
> then manages groups of clocks. We do not have drivers for it, so I am
> not sure how this here will work out.
> 
> I will grow the explanation in comment.
> 

Clocks can work without cesta block as well.

>>
>>> +       },
>>> +};
>>> +
>>> +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
>>> +       .cmd_rcgr = 0x8108,
>>> +       .mnd_width = 8,
>>> +       .hid_width = 5,
>>> +       .parent_map = disp_cc_parent_map_1,
>>> +       .freq_tbl = ftbl_disp_cc_esync0_clk_src,
>>> +       .clkr.hw.init = &(const struct clk_init_data) {
>>> +               .name = "disp_cc_mdss_pclk0_clk_src",
>>> +               .parent_data = disp_cc_parent_data_1,
>>> +               .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
>>> +               .flags = CLK_SET_RATE_PARENT,
>>> +               .ops = &clk_pixel_ops,
>>> +       },
>> [...]
>>> +               .enable_reg = 0x80b4,
>>> +               .enable_mask = BIT(0),
>>> +               .hw.init = &(const struct clk_init_data) {
>>> +                       .name = "disp_cc_osc_clk",
>>> +                       .parent_hws = (const struct clk_hw*[]) {
>>> +                               &disp_cc_osc_clk_src.clkr.hw,
>>> +                       },
>>> +                       .num_parents = 1,
>>> +                       .flags = CLK_SET_RATE_PARENT,
>>> +                       .ops = &clk_branch2_ops,
>>> +               },
>>> +       },
>>> +};
>>> +
>>> +static struct gdsc mdss_gdsc = {
>>> +       .gdscr = 0x9000,
>>> +       .en_rest_wait_val = 0x2,
>>> +       .en_few_wait_val = 0x2,
>>> +       .clk_dis_wait_val = 0xf,
>>> +       .pd = {
>>> +               .name = "mdss_gdsc",
>>> +       },
>>> +       .pwrsts = PWRSTS_OFF_ON,
>>> +       .flags = POLL_CFG_GDSCR | HW_CTRL | RETAIN_FF_ENABLE,
>>> +       // TODO: no supply?
>>
>> What is this?
> 
> Development note. I will clean it up.
> 
> 
> 
> Best regards,
> Krzysztof
> 

-- 
Thanks & Regards,
Taniya Das.