[PATCH v3 0/4] x86/mce: Add supports for Zhaoxin MCA

[PATCH v3 0/4] x86/mce: Add supports for Zhaoxin MCA

[Tony W Wang-oc]

Zhaoxin newer CPUs support MCE, CMCI and LMCE that compatible with
Intel's "Machine-Check Architecture".

To enable the supports of Linux kernel to Zhaoxin's MCA, add
specific patches for Zhaoxin's MCE, CMCI and LMCE. patches about
Zhaoxin's CMCI, LMCE use 3 functions in mce/intel.c, so make these
functions non-static.

Some Zhaoxin's CPUs have MCA bank 8, that only has one error called SVAD
(System View Address Decoder) which be controlled by IA32_MC8.CTL.0.
If enabled, the prefetch on these CPUs will cause SVAD machine check
exception when virtual machine startup and cause system panic. Add a
quirk for these Zhaoxin CPUs MCA bank 8.

v2->v3:
 - Make ifelse-case to switch-case (patch 1/4)
 - Simplify Zhaoxin CPU FMS checking (patch 1/4, 3/4)
 - Revert 1 unused function intel_ppin_init() (patch 2/4)
 - Rework mce_zhaoxin_feature_init() as static (patch 3/4)
 - Rework comment about Zhaoxin MCA SVAD and CMCI (patch 3/4)
 - Rework mce_zhaoxin_feature_clear() as static (patch 4/4)
 - Add comment and change coding style (patch 4/4)

v1->v2:
 - Fix redefinition of "mce_zhaoxin_feature_init" (patch 3/4)
 - Fix redefinition of "mce_zhaoxin_feature_clear" (patch 4/4)

TonyWWang-oc(4):
 x86/mce: Add Zhaoxin MCE support
 x86/mce: Make 3 functions non-static
 x86/mce: Add Zhaoxin CMCI support
 x86/mce: Add Zhaoxin LMCE support

 arch/x86/kernel/cpu/mce/core.c     | 98 +++++++++++++++++++++++++++++++++-----
 arch/x86/kernel/cpu/mce/intel.c    | 11 +++--
 arch/x86/kernel/cpu/mce/internal.h |  6 +++
 3 files changed, 99 insertions(+), 16 deletions(-)

-- 
2.7.4

Re: [PATCH v3 0/4] x86/mce: Add supports for Zhaoxin MCA

[Thomas Gleixner]

On Mon, 16 Sep 2019, Tony W Wang-oc wrote:

> Zhaoxin newer CPUs support MCE, CMCI and LMCE that compatible with
> Intel's "Machine-Check Architecture".

Thanks for providing a cover letter. Though threading does not work either
with that simply because the 1-4/4 mails lack a

   References: <Message-id-of-cover-letter>

tag. They have some weird:

   Thread-Index: AdVsgZ9UPwR7QKdtRlW4qXXe20fCvg==

tag, but that is different for every mail.

   Thread-Index: AdVsghaYSu2N9NgNSwS4zHAPRb3wjg==

'Thread-Index' is a MS Outlook specific header which is not supported by
real MUAs.

Please make sure to fix that when you are going to send the next round of
patches. Send them to yourself first and check the mail headers for a
proper References: tag chain. If you want to know how that looks just have
a look at the mail headers of any properly threaded patch series which you
received from LKML.

Thanks,

	tglx