[PATCH v2 0/5] x86/msr: Drop 32-bit interfaces of native MSR functions

[PATCH v2 0/5] x86/msr: Drop 32-bit interfaces of native MSR functions

[Juergen Gross]

Switch all users of the 32-bit native_*() MSR access functions to the
64-bit ones and drop the 32-bit interfaces.

Based on the series "x86/msr: Drop 32-bit MSR interfaces" [1].

[1]: https://lore.kernel.org/lkml/20260911074530.3140830-1-jgross@suse.com/T/#t

Changes in V2:
- small fix in patch 1
- rebased

Juergen Gross (5):
  x86/msr: Switch users of native_wrmsr() to native_wrmsrq()
  x86/msr: Remove native_wrmsr()
  x86/msr: Switch users of native_rdmsr() to native_rdmsrq()
  x86/msr: Remove native_rdmsr()
  x86/msr: Switch native_wrmsrq() from macro to inline function

 arch/x86/coco/sev/internal.h              |  7 +------
 arch/x86/include/asm/microcode.h          |  6 +-----
 arch/x86/include/asm/msr.h                | 16 ++++------------
 arch/x86/kernel/cpu/intel.c               |  6 +++---
 arch/x86/kernel/cpu/microcode/amd.c       |  4 ++--
 arch/x86/kernel/cpu/microcode/core.c      |  4 ++--
 arch/x86/kernel/cpu/resctrl/pseudo_lock.c |  4 ++--
 7 files changed, 15 insertions(+), 32 deletions(-)

-- 
2.55.0

[PATCH v2 1/5] x86/msr: Switch users of native_wrmsr() to native_wrmsrq()

[Juergen Gross]

Switch all users of native_wrmsr() to native_wrmsrq() in order to
prepare removal of native_wrmsr().

Signed-off-by: Juergen Gross <jgross@suse.com>
---
V2:
- switch order of hi and lo parts when oring them (Reinette Chatre)
---
 arch/x86/coco/sev/internal.h              | 7 +------
 arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++--
 2 files changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/x86/coco/sev/internal.h b/arch/x86/coco/sev/internal.h
index b9632c0fc391..2e2ff48a7aae 100644
--- a/arch/x86/coco/sev/internal.h
+++ b/arch/x86/coco/sev/internal.h
@@ -80,12 +80,7 @@ static inline u64 sev_es_rd_ghcb_msr(void)
 
 static __always_inline void sev_es_wr_ghcb_msr(u64 val)
 {
-	u32 low, high;
-
-	low  = (u32)(val);
-	high = (u32)(val >> 32);
-
-	native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high);
+	native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val);
 }
 
 enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write);
diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
index 0408ac7f66fd..a04cf26e0302 100644
--- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
+++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
@@ -175,7 +175,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
 	 * pseudo-locked followed by reading of kernel memory to load it
 	 * into the cache.
 	 */
-	native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid);
+	native_wrmsrq(MSR_IA32_PQR_ASSOC, rmid_p | ((u64)plr->closid << 32));
 
 	/*
 	 * Cache was flushed earlier. Now access kernel memory to read it
@@ -212,7 +212,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
 	 * Critical section end: restore closid with capacity bitmask that
 	 * does not overlap with pseudo-locked region.
 	 */
-	native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
+	native_wrmsrq(MSR_IA32_PQR_ASSOC, (u64)closid_p << 32 | rmid_p);
 
 	/* Re-enable the hardware prefetcher(s) */
 	wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr);
-- 
2.55.0

Re: [PATCH v2 1/5] x86/msr: Switch users of native_wrmsr() to native_wrmsrq()

[Reinette Chatre]

Hi Juergen

On 9/11/26 12:52 AM, Juergen Gross wrote:

...

> ---
> V2:
> - switch order of hi and lo parts when oring them (Reinette Chatre)
> ---

...

> diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
> index 0408ac7f66fd..a04cf26e0302 100644
> --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
> +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c
> @@ -175,7 +175,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
>  	 * pseudo-locked followed by reading of kernel memory to load it
>  	 * into the cache.
>  	 */
> -	native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid);
> +	native_wrmsrq(MSR_IA32_PQR_ASSOC, rmid_p | ((u64)plr->closid << 32));
>  
>  	/*
>  	 * Cache was flushed earlier. Now access kernel memory to read it
> @@ -212,7 +212,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr)
>  	 * Critical section end: restore closid with capacity bitmask that
>  	 * does not overlap with pseudo-locked region.
>  	 */
> -	native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p);
> +	native_wrmsrq(MSR_IA32_PQR_ASSOC, (u64)closid_p << 32 | rmid_p);
>  
>  	/* Re-enable the hardware prefetcher(s) */
>  	wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr);

Could both these hunks please use the same "high | low" pattern?

Thank you

Reinette

[PATCH v2 2/5] x86/msr: Remove native_wrmsr()

[Juergen Gross]

As native_wrmsr() has no users left, remove it.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/include/asm/msr.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 95761803c2e6..bfad2b96a892 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -95,9 +95,6 @@ static __always_inline u64 native_rdmsrq(u32 msr)
 	return __rdmsr(msr);
 }
 
-#define native_wrmsr(msr, low, high)			\
-	__wrmsrq((msr), (u64)(high) << 32 | (low))
-
 #define native_wrmsrq(msr, val)				\
 	__wrmsrq((msr), (val))
 
-- 
2.55.0

[PATCH v2 3/5] x86/msr: Switch users of native_rdmsr() to native_rdmsrq()

[Juergen Gross]

Switch all users of native_rdmsr() to native_rdmsrq() in order to
prepare removal of native_rdmsr().

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/include/asm/microcode.h     | 6 +-----
 arch/x86/kernel/cpu/intel.c          | 6 +++---
 arch/x86/kernel/cpu/microcode/amd.c  | 4 ++--
 arch/x86/kernel/cpu/microcode/core.c | 4 ++--
 4 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 645e65ac1586..6eef329def4b 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -64,17 +64,13 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd
 
 static inline u32 intel_get_microcode_revision(void)
 {
-	u32 rev, dummy;
-
 	native_wrmsrq(MSR_IA32_UCODE_REV, 0);
 
 	/* As documented in the SDM: Do a CPUID 1 here */
 	native_cpuid_eax(1);
 
 	/* get the current revision from MSR 0x8B */
-	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
-
-	return rev;
+	return native_rdmsrq(MSR_IA32_UCODE_REV) >> 32;
 }
 #endif /* !CONFIG_CPU_SUP_INTEL */
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 2aabe9affa0c..99474f160b86 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -214,7 +214,7 @@ static u32 intel_cpuid_vfm(void)
 
 u32 intel_get_platform_id(void)
 {
-	unsigned int val[2];
+	u64 val;
 
 	if (x86_hypervisor_present)
 		return 0;
@@ -229,9 +229,9 @@ u32 intel_get_platform_id(void)
 		return 0;
 
 	/* get processor flags from MSR 0x17 */
-	native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
+	val = native_rdmsrq(MSR_IA32_PLATFORM_ID);
 
-	return (val[1] >> 18) & 7;
+	return (val >> 50) & 7;
 }
 
 static void early_init_intel(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 6cdc410e7547..f6dc79dd18dd 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -315,7 +315,7 @@ static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val)
 
 static u32 get_patch_level(void)
 {
-	u32 rev, dummy __always_unused;
+	u32 rev;
 
 	if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present) {
 		int cpu = smp_processor_id();
@@ -332,7 +332,7 @@ static u32 get_patch_level(void)
 		return microcode_rev[cpu];
 	}
 
-	native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
+	rev = native_rdmsrq(MSR_AMD64_PATCH_LEVEL);
 	if (!rev) {
 		if (x86_family(bsp_cpuid_1_eax) < 0x17)
 			return rev;
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 0dd0c7241c57..ea696a202c31 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -94,13 +94,13 @@ struct early_load_data early_data;
  */
 static bool amd_check_current_patch_level(void)
 {
-	u32 lvl, dummy, i;
+	u32 lvl, i;
 	u32 *levels;
 
 	if (x86_cpuid_vendor() != X86_VENDOR_AMD)
 		return false;
 
-	native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy);
+	lvl = native_rdmsrq(MSR_AMD64_PATCH_LEVEL);
 
 	levels = final_levels;
 
-- 
2.55.0

[PATCH v2 4/5] x86/msr: Remove native_rdmsr()

[Juergen Gross]

As native_rdmsr() has no users left, remove it.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/include/asm/msr.h | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index bfad2b96a892..7bb5bf408fa6 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -83,13 +83,6 @@ static __always_inline void __wrmsrq(u32 msr, u64 val)
 		     : : "c" (msr), "a" ((u32)val), "d" ((u32)(val >> 32)) : "memory");
 }
 
-#define native_rdmsr(msr, val1, val2)			\
-do {							\
-	u64 __val = __rdmsr((msr));			\
-	(void)((val1) = (u32)__val);			\
-	(void)((val2) = (u32)(__val >> 32));		\
-} while (0)
-
 static __always_inline u64 native_rdmsrq(u32 msr)
 {
 	return __rdmsr(msr);
-- 
2.55.0

[PATCH v2 5/5] x86/msr: Switch native_wrmsrq() from macro to inline function

[Juergen Gross]

Make native_wrmsrq() an inline function.

Signed-off-by: Juergen Gross <jgross@suse.com>
---
 arch/x86/include/asm/msr.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 7bb5bf408fa6..3b33d432bc24 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -88,8 +88,10 @@ static __always_inline u64 native_rdmsrq(u32 msr)
 	return __rdmsr(msr);
 }
 
-#define native_wrmsrq(msr, val)				\
-	__wrmsrq((msr), (val))
+static __always_inline void native_wrmsrq(u32 msr, u64 val)
+{
+	__wrmsrq(msr, val);
+}
 
 static inline u64 native_read_msr(u32 msr)
 {
-- 
2.55.0