* [PATCH RESEND v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU
2024-12-13 11:31 [PATCH RESEND v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
@ 2024-12-13 11:31 ` Akhil P Oommen
2024-12-16 9:33 ` Krzysztof Kozlowski
2024-12-13 11:31 ` [PATCH RESEND v2 2/4] dt-bindings: display/msm/gmu: Document RGMU Akhil P Oommen
` (2 subsequent siblings)
3 siblings, 1 reply; 12+ messages in thread
From: Akhil P Oommen @ 2024-12-13 11:31 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen
A612 GPU requires an additional smmu_vote clock. Update the bindings to
reflect this.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
.../devicetree/bindings/display/msm/gpu.yaml | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 6ddc72fd85b04537ea270754a897b4e7eb269641..1276331cb262e64cc94d6a9973463b3c1ff8b7a8 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -217,6 +217,42 @@ allOf:
required:
- clocks
- clock-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,adreno-612.0
+ then:
+ properties:
+ clocks:
+ minItems: 5
+ maxItems: 5
+
+ clock-names:
+ items:
+ - const: core
+ description: GPU Core clock
+ - const: mem_iface
+ description: GPU Memory Interface clock
+ - const: alt_mem_iface
+ description: GPU Alternative Memory Interface clock
+ - const: gmu
+ description: CX GMU clock
+ - const: xo
+ description: GPUCC clocksource clock
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_dbgc
+
+ required:
+ - clocks
+ - clock-names
+
else:
if:
properties:
--
2.45.2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH RESEND v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU
2024-12-13 11:31 ` [PATCH RESEND v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
@ 2024-12-16 9:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2024-12-16 9:33 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On Fri, Dec 13, 2024 at 05:01:03PM +0530, Akhil P Oommen wrote:
> A612 GPU requires an additional smmu_vote clock. Update the bindings to
> reflect this.
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> .../devicetree/bindings/display/msm/gpu.yaml | 36 ++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> index 6ddc72fd85b04537ea270754a897b4e7eb269641..1276331cb262e64cc94d6a9973463b3c1ff8b7a8 100644
> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
> @@ -217,6 +217,42 @@ allOf:
> required:
> - clocks
> - clock-names
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - qcom,adreno-612.0
> + then:
> + properties:
> + clocks:
> + minItems: 5
> + maxItems: 5
> +
> + clock-names:
> + items:
> + - const: core
> + description: GPU Core clock
> + - const: mem_iface
> + description: GPU Memory Interface clock
> + - const: alt_mem_iface
> + description: GPU Alternative Memory Interface clock
> + - const: gmu
> + description: CX GMU clock
> + - const: xo
> + description: GPUCC clocksource clock
> +
Missing constraints for reg. xxx and xxx-names cannot be different.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH RESEND v2 2/4] dt-bindings: display/msm/gmu: Document RGMU
2024-12-13 11:31 [PATCH RESEND v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
2024-12-13 11:31 ` [PATCH RESEND v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
@ 2024-12-13 11:31 ` Akhil P Oommen
2024-12-16 9:39 ` Krzysztof Kozlowski
2024-12-13 11:31 ` [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
2024-12-13 11:31 ` [PATCH RESEND v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
3 siblings, 1 reply; 12+ messages in thread
From: Akhil P Oommen @ 2024-12-13 11:31 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen
RGMU a.k.a Reduced Graphics Management Unit is a small state machine
with the sole purpose of providing IFPC support. Compared to GMU, it
doesn't manage GPU clock, voltage scaling, bw voting or any other
functionalities. All it does is detect an idle GPU and toggle the
GDSC switch. So it doesn't require iommu & opp table.
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index b1bd372996d57138a0e80f8d93df09943775fdfa..6889dda7d4be71535dff1a62ca30f980bfc6128d 100644
--- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
@@ -27,6 +27,7 @@ properties:
- pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- const: qcom,adreno-gmu-wrapper
+ - const: qcom,adreno-rgmu
reg:
minItems: 1
@@ -267,12 +268,14 @@ allOf:
properties:
compatible:
contains:
- const: qcom,adreno-gmu-wrapper
+ enum:
+ - qcom,adreno-gmu-wrapper
+ - qcom,adreno-rgmu
then:
properties:
reg:
items:
- - description: GMU wrapper register space
+ - description: RGMU/GMU wrapper register space
reg-names:
items:
- const: gmu
--
2.45.2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH RESEND v2 2/4] dt-bindings: display/msm/gmu: Document RGMU
2024-12-13 11:31 ` [PATCH RESEND v2 2/4] dt-bindings: display/msm/gmu: Document RGMU Akhil P Oommen
@ 2024-12-16 9:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 12+ messages in thread
From: Krzysztof Kozlowski @ 2024-12-16 9:39 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On Fri, Dec 13, 2024 at 05:01:04PM +0530, Akhil P Oommen wrote:
> RGMU a.k.a Reduced Graphics Management Unit is a small state machine
> with the sole purpose of providing IFPC support. Compared to GMU, it
What is IFPC?
> doesn't manage GPU clock, voltage scaling, bw voting or any other
> functionalities. All it does is detect an idle GPU and toggle the
> GDSC switch. So it doesn't require iommu & opp table.
>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> Documentation/devicetree/bindings/display/msm/gmu.yaml | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> index b1bd372996d57138a0e80f8d93df09943775fdfa..6889dda7d4be71535dff1a62ca30f980bfc6128d 100644
> --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml
> @@ -27,6 +27,7 @@ properties:
> - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
> - const: qcom,adreno-gmu
> - const: qcom,adreno-gmu-wrapper
> + - const: qcom,adreno-rgmu
>
> reg:
> minItems: 1
> @@ -267,12 +268,14 @@ allOf:
> properties:
> compatible:
> contains:
> - const: qcom,adreno-gmu-wrapper
> + enum:
> + - qcom,adreno-gmu-wrapper
> + - qcom,adreno-rgmu
Does your new rgmu has clocks, interrupts etc? If yes, define them. If
not, disallow them.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-13 11:31 [PATCH RESEND v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
2024-12-13 11:31 ` [PATCH RESEND v2 1/4] dt-bindings: display/msm: gpu: Document A612 GPU Akhil P Oommen
2024-12-13 11:31 ` [PATCH RESEND v2 2/4] dt-bindings: display/msm/gmu: Document RGMU Akhil P Oommen
@ 2024-12-13 11:31 ` Akhil P Oommen
2024-12-13 15:09 ` Konrad Dybcio
2025-01-08 22:33 ` Bjorn Andersson
2024-12-13 11:31 ` [PATCH RESEND v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
3 siblings, 2 replies; 12+ messages in thread
From: Akhil P Oommen @ 2024-12-13 11:31 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen, Jie Zhang
From: Jie Zhang <quic_jiezh@quicinc.com>
Add gpu and gmu nodes for qcs615 chipset.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..dee5d3be4aa34dd64864b6fe32ad589abac99bb7 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -387,6 +387,11 @@ smem_region: smem@86000000 {
no-map;
hwlocks = <&tcsr_mutex 3>;
};
+
+ pil_gpu_mem: pil-gpu@97715000 {
+ reg = <0x0 0x97715000 0x0 0x2000>;
+ no-map;
+ };
};
soc: soc@0 {
@@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state {
};
};
+ gpu: gpu@5000000 {
+ compatible = "qcom,adreno-612.0", "qcom,adreno";
+ reg = <0x0 0x05000000 0x0 0x90000>;
+ reg-names = "kgsl_3d0_reg_memory";
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>;
+ clock-names = "core",
+ "mem_iface",
+ "alt_mem_iface",
+ "gmu",
+ "xo";
+
+ interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0x0 0x401>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
+ qcom,gmu = <&rgmu>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&pil_gpu_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-435000000 {
+ opp-hz = /bits/ 64 <435000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ opp-peak-kBps = <3000000>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ opp-peak-kBps = <3975000>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ opp-peak-kBps = <5287500>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ opp-peak-kBps = <6075000>;
+ };
+
+ opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ required-opps = <&rpmhpd_opp_turbo>;
+ opp-peak-kBps = <7050000>;
+ };
+ };
+ };
+
+ rgmu: rgmu@506a000 {
+ compatible = "qcom,adreno-rgmu";
+ reg = <0x0 0x0506a000 0x0 0x34000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc CX_GDSC>,
+ <&gpucc GX_GDSC>;
+ power-domain-names = "cx", "gx";
+
+ interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hfi", "gmu";
+ };
+
gpucc: clock-controller@5090000 {
compatible = "qcom,qcs615-gpucc";
reg = <0 0x5090000 0 0x9000>;
--
2.45.2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-13 11:31 ` [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
@ 2024-12-13 15:09 ` Konrad Dybcio
2024-12-13 15:10 ` Konrad Dybcio
2025-01-08 22:33 ` Bjorn Andersson
1 sibling, 1 reply; 12+ messages in thread
From: Konrad Dybcio @ 2024-12-13 15:09 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel, Jie Zhang
On 13.12.2024 12:31 PM, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and gmu nodes for qcs615 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-13 15:09 ` Konrad Dybcio
@ 2024-12-13 15:10 ` Konrad Dybcio
0 siblings, 0 replies; 12+ messages in thread
From: Konrad Dybcio @ 2024-12-13 15:10 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Abhinav Kumar, Dmitry Baryshkov, Marijn Suijten,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel, Jie Zhang
On 13.12.2024 4:09 PM, Konrad Dybcio wrote:
> On 13.12.2024 12:31 PM, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_jiezh@quicinc.com>
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Well I forgot I made comments on the non-resend version
https://lore.kernel.org/linux-arm-msm/a44027ee-40d3-4552-8f61-bcab77476f68@oss.qualcomm.com/
Konrad
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2024-12-13 11:31 ` [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
2024-12-13 15:09 ` Konrad Dybcio
@ 2025-01-08 22:33 ` Bjorn Andersson
2025-01-08 22:45 ` Akhil P Oommen
1 sibling, 1 reply; 12+ messages in thread
From: Bjorn Andersson @ 2025-01-08 22:33 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, Jie Zhang
On Fri, Dec 13, 2024 at 05:01:05PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Add gpu and gmu nodes for qcs615 chipset.
>
Please resubmit this in a series together with the gpucc patch.
Regards,
Bjorn
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..dee5d3be4aa34dd64864b6fe32ad589abac99bb7 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -387,6 +387,11 @@ smem_region: smem@86000000 {
> no-map;
> hwlocks = <&tcsr_mutex 3>;
> };
> +
> + pil_gpu_mem: pil-gpu@97715000 {
> + reg = <0x0 0x97715000 0x0 0x2000>;
> + no-map;
> + };
> };
>
> soc: soc@0 {
> @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state {
> };
> };
>
> + gpu: gpu@5000000 {
> + compatible = "qcom,adreno-612.0", "qcom,adreno";
> + reg = <0x0 0x05000000 0x0 0x90000>;
> + reg-names = "kgsl_3d0_reg_memory";
> +
> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
> + <&gpucc GPU_CC_CX_GMU_CLK>,
> + <&gpucc GPU_CC_CXO_CLK>;
> + clock-names = "core",
> + "mem_iface",
> + "alt_mem_iface",
> + "gmu",
> + "xo";
> +
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "gfx-mem";
> +
> + iommus = <&adreno_smmu 0x0 0x401>;
> + operating-points-v2 = <&gpu_opp_table>;
> + power-domains = <&rpmhpd RPMHPD_CX>;
> + qcom,gmu = <&rgmu>;
> +
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_zap_shader: zap-shader {
> + memory-region = <&pil_gpu_mem>;
> + };
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-435000000 {
> + opp-hz = /bits/ 64 <435000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + opp-peak-kBps = <3000000>;
> + };
> +
> + opp-500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + opp-peak-kBps = <3975000>;
> + };
> +
> + opp-650000000 {
> + opp-hz = /bits/ 64 <650000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + opp-peak-kBps = <5287500>;
> + };
> +
> + opp-745000000 {
> + opp-hz = /bits/ 64 <745000000>;
> + required-opps = <&rpmhpd_opp_nom_l1>;
> + opp-peak-kBps = <6075000>;
> + };
> +
> + opp-845000000 {
> + opp-hz = /bits/ 64 <845000000>;
> + required-opps = <&rpmhpd_opp_turbo>;
> + opp-peak-kBps = <7050000>;
> + };
> + };
> + };
> +
> + rgmu: rgmu@506a000 {
> + compatible = "qcom,adreno-rgmu";
> + reg = <0x0 0x0506a000 0x0 0x34000>;
> + reg-names = "gmu";
> + power-domains = <&gpucc CX_GDSC>,
> + <&gpucc GX_GDSC>;
> + power-domain-names = "cx", "gx";
> +
> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hfi", "gmu";
> + };
> +
> gpucc: clock-controller@5090000 {
> compatible = "qcom,qcs615-gpucc";
> reg = <0 0x5090000 0 0x9000>;
>
> --
> 2.45.2
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes
2025-01-08 22:33 ` Bjorn Andersson
@ 2025-01-08 22:45 ` Akhil P Oommen
0 siblings, 0 replies; 12+ messages in thread
From: Akhil P Oommen @ 2025-01-08 22:45 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm,
dri-devel, freedreno, devicetree, linux-kernel, Jie Zhang
On 1/9/2025 4:03 AM, Bjorn Andersson wrote:
> On Fri, Dec 13, 2024 at 05:01:05PM +0530, Akhil P Oommen wrote:
>> From: Jie Zhang <quic_jiezh@quicinc.com>
>>
>> Add gpu and gmu nodes for qcs615 chipset.
>>
>
> Please resubmit this in a series together with the gpucc patch.
Sure. I will send a new revision.
-Akhil.
>
> Regards,
> Bjorn
>
>> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/qcs615.dtsi | 88 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 88 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 8df26efde3fd6c0f85b9bcddb461fae33687dc75..dee5d3be4aa34dd64864b6fe32ad589abac99bb7 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -387,6 +387,11 @@ smem_region: smem@86000000 {
>> no-map;
>> hwlocks = <&tcsr_mutex 3>;
>> };
>> +
>> + pil_gpu_mem: pil-gpu@97715000 {
>> + reg = <0x0 0x97715000 0x0 0x2000>;
>> + no-map;
>> + };
>> };
>>
>> soc: soc@0 {
>> @@ -508,6 +513,89 @@ qup_uart0_rx: qup-uart0-rx-state {
>> };
>> };
>>
>> + gpu: gpu@5000000 {
>> + compatible = "qcom,adreno-612.0", "qcom,adreno";
>> + reg = <0x0 0x05000000 0x0 0x90000>;
>> + reg-names = "kgsl_3d0_reg_memory";
>> +
>> + clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
>> + <&gcc GCC_DDRSS_GPU_AXI_CLK>,
>> + <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
>> + <&gpucc GPU_CC_CX_GMU_CLK>,
>> + <&gpucc GPU_CC_CXO_CLK>;
>> + clock-names = "core",
>> + "mem_iface",
>> + "alt_mem_iface",
>> + "gmu",
>> + "xo";
>> +
>> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
>> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
>> + interconnect-names = "gfx-mem";
>> +
>> + iommus = <&adreno_smmu 0x0 0x401>;
>> + operating-points-v2 = <&gpu_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_CX>;
>> + qcom,gmu = <&rgmu>;
>> +
>> + #cooling-cells = <2>;
>> +
>> + status = "disabled";
>> +
>> + gpu_zap_shader: zap-shader {
>> + memory-region = <&pil_gpu_mem>;
>> + };
>> +
>> + gpu_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-435000000 {
>> + opp-hz = /bits/ 64 <435000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + opp-peak-kBps = <3000000>;
>> + };
>> +
>> + opp-500000000 {
>> + opp-hz = /bits/ 64 <500000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + opp-peak-kBps = <3975000>;
>> + };
>> +
>> + opp-650000000 {
>> + opp-hz = /bits/ 64 <650000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + opp-peak-kBps = <5287500>;
>> + };
>> +
>> + opp-745000000 {
>> + opp-hz = /bits/ 64 <745000000>;
>> + required-opps = <&rpmhpd_opp_nom_l1>;
>> + opp-peak-kBps = <6075000>;
>> + };
>> +
>> + opp-845000000 {
>> + opp-hz = /bits/ 64 <845000000>;
>> + required-opps = <&rpmhpd_opp_turbo>;
>> + opp-peak-kBps = <7050000>;
>> + };
>> + };
>> + };
>> +
>> + rgmu: rgmu@506a000 {
>> + compatible = "qcom,adreno-rgmu";
>> + reg = <0x0 0x0506a000 0x0 0x34000>;
>> + reg-names = "gmu";
>> + power-domains = <&gpucc CX_GDSC>,
>> + <&gpucc GX_GDSC>;
>> + power-domain-names = "cx", "gx";
>> +
>> + interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "hfi", "gmu";
>> + };
>> +
>> gpucc: clock-controller@5090000 {
>> compatible = "qcom,qcs615-gpucc";
>> reg = <0 0x5090000 0 0x9000>;
>>
>> --
>> 2.45.2
>>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH RESEND v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
2024-12-13 11:31 [PATCH RESEND v2 0/4] Devicetree changes for QCS615's GPU Akhil P Oommen
` (2 preceding siblings ...)
2024-12-13 11:31 ` [PATCH RESEND v2 3/4] arm64: dts: qcom: qcs615: Add gpu and gmu nodes Akhil P Oommen
@ 2024-12-13 11:31 ` Akhil P Oommen
2024-12-13 13:31 ` Dmitry Baryshkov
3 siblings, 1 reply; 12+ messages in thread
From: Akhil P Oommen @ 2024-12-13 11:31 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Dmitry Baryshkov, Marijn Suijten, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Akhil P Oommen, Jie Zhang
From: Jie Zhang <quic_jiezh@quicinc.com>
Enable GPU for qcs615-ride platform and provide path for zap
shader.
Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
---
arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index ee6cab3924a6d71f29934a8debba3a832882abdd..860a0db1908cfe32a250b14aac14065923c5a575 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -202,6 +202,14 @@ &gcc {
<&sleep_clk>;
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/qcs615/a612_zap.mbn";
+};
+
&qupv3_id_0 {
status = "okay";
};
--
2.45.2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH RESEND v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU
2024-12-13 11:31 ` [PATCH RESEND v2 4/4] arm64: dts: qcom: qcs615-ride: Enable Adreno 612 GPU Akhil P Oommen
@ 2024-12-13 13:31 ` Dmitry Baryshkov
0 siblings, 0 replies; 12+ messages in thread
From: Dmitry Baryshkov @ 2024-12-13 13:31 UTC (permalink / raw)
To: Akhil P Oommen
Cc: Rob Clark, Sean Paul, Konrad Dybcio, Abhinav Kumar,
Marijn Suijten, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Jie Zhang
On Fri, 13 Dec 2024 at 13:32, Akhil P Oommen <quic_akhilpo@quicinc.com> wrote:
>
> From: Jie Zhang <quic_jiezh@quicinc.com>
>
> Enable GPU for qcs615-ride platform and provide path for zap
> shader.
>
> Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> index ee6cab3924a6d71f29934a8debba3a832882abdd..860a0db1908cfe32a250b14aac14065923c5a575 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
> @@ -202,6 +202,14 @@ &gcc {
> <&sleep_clk>;
> };
>
> +&gpu {
> + status = "okay";
> +};
> +
> +&gpu_zap_shader {
> + firmware-name = "qcom/qcs615/a612_zap.mbn";
This brings up my usual question: should it be qcom/qcs615 (fine with
me) or qcom/sm6150 (maybe even better?)
> +};
> +
> &qupv3_id_0 {
> status = "okay";
> };
>
> --
> 2.45.2
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 12+ messages in thread