Re: [PATCH v4 1/2] arm64: dts: mediatek: mt8195: add efuse node and cells

[Matthias Brugger <matthias.bgg@gmail.com>]

Series applied, thanks!

On 17/06/2022 09:23, Chunfeng Yun wrote:
> Add efuse node and cells used by t-phy to fix the bit shift issue
> 
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Macpaul Lin <macpaul.lin@mediatek.com>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v4: no changes
> 
> v3:
>    add reviewed-by and tested-by;
>    fix duplicated unit-address warning;
> 
> NOTE:
>    based on v5.18-next/dts64 of matthias.bgg's branch;
> 
> v2: no changes, just based on new mt8195.dtsi
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 55 ++++++++++++++++++++++++
>   1 file changed, 55 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b57e620c2c72..d5bc4cf5f4ac 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -691,6 +691,53 @@
>   			status = "disabled";
>   		};
>   
> +		efuse: efuse@11c10000 {
> +			compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
> +			reg = <0 0x11c10000 0 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			u3_tx_imp_p0: usb3-tx-imp@184,1 {
> +				reg = <0x184 0x1>;
> +				bits = <0 5>;
> +			};
> +			u3_rx_imp_p0: usb3-rx-imp@184,2 {
> +				reg = <0x184 0x2>;
> +				bits = <5 5>;
> +			};
> +			u3_intr_p0: usb3-intr@185 {
> +				reg = <0x185 0x1>;
> +				bits = <2 6>;
> +			};
> +			comb_tx_imp_p1: usb3-tx-imp@186,1 {
> +				reg = <0x186 0x1>;
> +				bits = <0 5>;
> +			};
> +			comb_rx_imp_p1: usb3-rx-imp@186,2 {
> +				reg = <0x186 0x2>;
> +				bits = <5 5>;
> +			};
> +			comb_intr_p1: usb3-intr@187 {
> +				reg = <0x187 0x1>;
> +				bits = <2 6>;
> +			};
> +			u2_intr_p0: usb2-intr-p0@188,1 {
> +				reg = <0x188 0x1>;
> +				bits = <0 5>;
> +			};
> +			u2_intr_p1: usb2-intr-p1@188,2 {
> +				reg = <0x188 0x2>;
> +				bits = <5 5>;
> +			};
> +			u2_intr_p2: usb2-intr-p2@189,1 {
> +				reg = <0x189 0x1>;
> +				bits = <2 5>;
> +			};
> +			u2_intr_p3: usb2-intr-p3@189,2 {
> +				reg = <0x189 0x2>;
> +				bits = <7 5>;
> +			};
> +		};
> +
>   		u3phy2: t-phy@11c40000 {
>   			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
>   			#address-cells = <1>;
> @@ -873,6 +920,10 @@
>   				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
>   					 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
>   				clock-names = "ref", "da_ref";
> +				nvmem-cells = <&comb_intr_p1>,
> +					      <&comb_rx_imp_p1>,
> +					      <&comb_tx_imp_p1>;
> +				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
>   				#phy-cells = <1>;
>   			};
>   		};
> @@ -897,6 +948,10 @@
>   				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
>   					 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
>   				clock-names = "ref", "da_ref";
> +				nvmem-cells = <&u3_intr_p0>,
> +					      <&u3_rx_imp_p0>,
> +					      <&u3_tx_imp_p0>;
> +				nvmem-cell-names = "intr", "rx_imp", "tx_imp";
>   				#phy-cells = <1>;
>   			};
>   		};