* Re: fast communication problem
2005-11-16 15:43 fast communication problem Ivan Korzakow
@ 2005-11-16 16:10 ` linux-os (Dick Johnson)
0 siblings, 0 replies; 2+ messages in thread
From: linux-os (Dick Johnson) @ 2005-11-16 16:10 UTC (permalink / raw)
To: Ivan Korzakow; +Cc: linux-kernel
On Wed, 16 Nov 2005, Ivan Korzakow wrote:
> Hi List,
>
> I'm running a 2.6.14 linux on 96 MHz MIPS processor. I need to cope
> with a device that sends a byte of data every 50 microsecond through
> an UART with no FIFO. What would be the best (well, the least
> horrible) way to handle that ? The good point is that I know when the
> communication starts.
>
> Any idea, any help, any "good luck" will be much appreciated !
>
> Thanks in advance,
>
> Ivan
Linux can handle interrupts at 100 microsecond intervals with
an ix86 of 400 MHz or above. The MIPS is supposed to be superb for
this kind of operation so you may not have a problem at 50 us and
90 MHz.
The hardware engineers here do know something so they would
never design something that needed the CPU at 50 microsecond
intervals --yet, although there are some new kids coming out
of school that haven't a clue and might create a requirement
like yours in the future!
The interrupt code must be well thought out, with the minimum
overhead of getting a byte from your buffer and writing it to
the device.
Use fixed buffers, probably ping/pong, so you don't have to
allocate anything in the ISR. If it doesn't work, then
call the hardware engineers the idiots they are after
instrumenting the reason why it won't work (takes 80
microseconds just to get to the ISR, leaving negative
time to do the work). They do everything in FPGAs nowadays.
If they buffered just one byte, you get interrupted every
100 us, 4 bytes 200 us, etc. Every bit helps.
Cheers,
Dick Johnson
Penguin : Linux version 2.6.13.4 on an i686 machine (5589.51 BogoMips).
Warning : 98.36% of all statistics are fiction.
.
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