From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Leo Yan <leo.yan@arm.com>, Mike Leach <mike.leach@arm.com>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Tamas Petz <tamas.petz@arm.com>,
Tamas Zsoldos <tamas.zsoldos@arm.com>,
Suyash Mahar <smahar@meta.com>, Amir Ayupov <aaupov@fb.com>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, coresight@lists.linaro.org
Subject: Re: [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites
Date: Mon, 9 Nov 2026 22:51:30 +0000 [thread overview]
Message-ID: <a79a52db-2361-4303-9d43-87837f349f48@arm.com> (raw)
In-Reply-To: <20261016-trbe_enable_disable_irq_handle_refactor-v2-9-3f57cf3199b1@arm.com>
On 16/10/2026 17:55, Leo Yan wrote:
> TRBSR_EL1 records the status of the buffer that just stopped. Clearing
> it in trbe_enable_hw() postpones cleanup until another run starts. If
> AUX output cannot restart, for example when AUX space is exhausted,
> that clear never executes. Clear the status in arm_trbe_disable()
> after disabling TRBE instead.
>
> trbe_handle_overflow() can start the next run without calling
> arm_trbe_disable(). Clear the stopped buffer's syndrome and status bits
> while TRBE is disabled, before attempting the AUX restart. This also
> leaves the status clean when the restart fails.
>
> Signed-off-by: Leo Yan <leo.yan@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-trbe.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
> index 26e7554d6bdd31f8a55a8bc3a7b6d4c49b984b9b..dd9c9330bb0c739795f300dafc6ce34e72fbf280 100644
> --- a/drivers/hwtracing/coresight/coresight-trbe.c
> +++ b/drivers/hwtracing/coresight/coresight-trbe.c
> @@ -655,7 +655,6 @@ static void trbe_enable_hw(struct trbe_buf *buf)
> WARN_ON(buf->trbe_hw_base < buf->trbe_base);
> WARN_ON(buf->trbe_write < buf->trbe_hw_base);
> WARN_ON(buf->trbe_write >= buf->trbe_limit);
> - clr_trbe_status();
TRBSR_ELx is UNKNOWN at reset and if we don't clear it at probe time, we
endup running the first session with unknown values. It is safer to
clear this at enable_hw.
Suzuki
> set_trbe_base_pointer(buf->trbe_hw_base);
> set_trbe_write_pointer(buf->trbe_write);
>
> @@ -1069,6 +1068,8 @@ static int arm_trbe_disable(struct coresight_device *csdev)
> return -EINVAL;
>
> trbe_drain_and_disable_local(cpudata);
> + clr_trbe_status();
> +
> buf->cpudata = NULL;
> cpudata->buf = NULL;
> cpudata->mode = CS_MODE_DISABLED;
> @@ -1095,6 +1096,13 @@ static int trbe_handle_overflow(struct perf_output_handle *handle)
> unsigned long size;
> struct etm_event_data *event_data;
>
> + /*
> + * Clear the status. No context synchronization is required here,
> + * since context synchronization will be performed before TRBE is
> + * re-enabled (see trbe_enable_hw()).
> + */
> + clr_trbe_status();
> +
> size = trbe_get_trace_size(handle, buf, true);
> if (buf->snapshot)
> handle->head += size;
>
next prev parent reply other threads:[~2026-11-09 22:51 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 16:54 [PATCH v2 00/23] coresight: trbe: Refactor buffer and IRQ handling Leo Yan
2026-10-16 16:54 ` [PATCH v2 01/23] arm64/sysreg: Define TRBSR_EL1.EC event classes Leo Yan
2026-10-16 16:55 ` [PATCH v2 02/23] coresight: trbe: Make watermark range check overflow safe in __trbe_normal_offset() Leo Yan
2026-10-16 16:55 ` [PATCH v2 03/23] coresight: trbe: Use helpers for checking errata Leo Yan
2026-10-16 16:55 ` [PATCH v2 04/23] coresight: trbe: Check the buffer association before IRQ validation Leo Yan
2026-10-16 16:55 ` [PATCH v2 05/23] coresight: trbe: Validate perf handle before using sink data Leo Yan
2026-10-16 16:55 ` [PATCH v2 06/23] coresight: trbe: Drop redundant disable from enable path Leo Yan
2026-11-09 16:27 ` James Clark
2026-10-16 16:55 ` [PATCH v2 07/23] coresight: trbe: Publish the session after successful enable Leo Yan
2026-10-16 16:55 ` [PATCH v2 08/23] coresight: trbe: Clear stale external abort status Leo Yan
2026-10-16 16:55 ` [PATCH v2 09/23] coresight: trbe: Clear TRBSR status at stop sites Leo Yan
2026-11-09 16:40 ` James Clark
2026-11-09 16:51 ` James Clark
2026-11-09 22:51 ` Suzuki K Poulose [this message]
2026-10-16 16:55 ` [PATCH v2 10/23] coresight: trbe: Drop redundant disables Leo Yan
2026-10-16 16:55 ` [PATCH v2 11/23] coresight: trbe: Assign the perf handle in enable and disable Leo Yan
2026-10-16 16:55 ` [PATCH v2 12/23] coresight: trbe: Decode TRBSR status codes Leo Yan
2026-10-16 16:55 ` [PATCH v2 13/23] coresight: trbe: Simplify wrap status handling Leo Yan
2026-10-16 16:55 ` [PATCH v2 14/23] coresight: trbe: Treat access not allowed stops as fatal Leo Yan
2026-10-16 16:55 ` [PATCH v2 15/23] coresight: trbe: Report truncated trace on buffer update errors Leo Yan
2026-10-16 16:55 ` [PATCH v2 16/23] coresight: trbe: Always classify TRBSR when updating buffer Leo Yan
2026-10-16 16:55 ` [PATCH v2 17/23] coresight: trbe: Calculate trace size across buffer wrap Leo Yan
2026-10-16 16:55 ` [PATCH v2 18/23] coresight: trbe: Keep the perf handle in per-CPU data Leo Yan
2026-10-16 16:55 ` [PATCH v2 19/23] coresight: trbe: Reload the AUX buffer on overflow restart Leo Yan
2026-10-16 16:55 ` [PATCH v2 20/23] coresight: trbe: Add fault action argument to trbe_handle_overflow() Leo Yan
2026-10-16 16:55 ` [PATCH v2 21/23] coresight: trbe: Read TRBSR after prohibiting and flushing trace Leo Yan
2026-10-16 16:55 ` [PATCH v2 22/23] coresight: trbe: Restart trace source for stopped buffers Leo Yan
2026-10-16 16:55 ` [PATCH v2 23/23] coresight: trbe: Report trace gaps with PARTIAL instead of COLLISION Leo Yan
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