Re: [PATCH 4/4] arm64: dts: qcom: sm8750: Add LLCC node

[Melody Olvera <quic_molvera@quicinc.com>]

On 1/14/2025 2:59 AM, Dmitry Baryshkov wrote:
> On Mon, Jan 13, 2025 at 01:26:43PM -0800, Melody Olvera wrote:
>> Add LLCC node for SM8750 SoC.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8750.dtsi | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index 3bbd7d18598ee0a3a0d5130c03a3166e1fc14d82..3cd7b40bdde68ac00c3dbe7fb3f20ebb2ba27045 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -2888,6 +2888,17 @@ gem_noc: interconnect@24100000 {
>>   			#interconnect-cells = <2>;
>>   		};
>>   
>> +		cache-controller@24800000 {
>> +			compatible = "qcom,sm8750-llcc";
>> +			reg = <0x0 0x24800000 0x0 0x200000>, <0x0 0x25800000 0x0 0x200000>,
>> +				<0x0 0x24C00000 0x0 0x200000>, <0x0 0x25C00000 0x0 0x200000>,
>> +				<0x0 0x26800000 0x0 0x200000>, <0x0 0x26C00000 0x0 0x200000>;
>> +			reg-names = "llcc0_base", "llcc1_base",
>> +				"llcc2_base", "llcc3_base",
>> +				"llcc_broadcast_base", "llcc_broadcast_and_base";
>> +			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
> PLease take a look at sm8650 and change your patch accordingly.
>
> NAK

Apologies; the contents of this patch are very similar to sm8650, just 
different offsets.
Only major diffs I see here are the node namde (cache-controller vs 
system-cache-controller)
and the formatting (two regs/line vs one reg/line). Is there anything 
else you mean by
this comment that I'm missing?

Thanks,
Melody

>
>> +
>>   		nsp_noc: interconnect@320c0000 {
>>   			compatible = "qcom,sm8750-nsp-noc";
>>   			reg = <0x0 0x320c0000 0x0 0x13080>;
>>
>> -- 
>> 2.46.1
>>