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From: "Arnd Bergmann" <arnd@arndb.de>
To: "Yushan Wang" <wangyushan12@huawei.com>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	"Drew Fustini" <fustini@kernel.org>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Will Deacon" <will@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Cc: fanghao11@huawei.com, linuxarm@huawei.com,
	liuyonglong@huawei.com, prime.zeng@hisilicon.com,
	"Zhou Wang" <wangzhou1@hisilicon.com>,
	"Wei Xu" <xuwei5@hisilicon.com>
Subject: Re: [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC
Date: Tue, 03 Feb 2026 18:19:25 +0100	[thread overview]
Message-ID: <a8ba1c0b-e7c8-44c5-b785-42752f7f5d8f@app.fastmail.com> (raw)
In-Reply-To: <20260203161843.649417-2-wangyushan12@huawei.com>

On Tue, Feb 3, 2026, at 17:18, Yushan Wang wrote:
> The driver will create a file of `/dev/hisi_l3c` on init, mmap
> operations to it will allocate a memory region that is guaranteed to be
> placed in L3 cache.
>
> The driver also provides unmap() to deallocated the locked memory.
>
> The driver also provides an ioctl interface for user to get cache lock
> information, such as lock restrictions and locked sizes.
>
> Signed-off-by: Yushan Wang <wangyushan12@huawei.com>

Hi Yushan,

Thanks for your submission. Since we are in the last week of
the merge window, this is not going to be linux-7.0 material,
but I'll have a quick look for now.

>  .../userspace-api/ioctl/ioctl-number.rst      |   1 +
>  MAINTAINERS                                   |   6 +
>  drivers/soc/hisilicon/Kconfig                 |  11 +
>  drivers/soc/hisilicon/Makefile                |   2 +
>  drivers/soc/hisilicon/hisi_soc_l3c.c          | 357 ++++++++++++++++++
>  include/uapi/misc/hisi_l3c.h                  |  28 ++

I don't think this should be in drivers/soc/, since I want
to reserve that for internal drivers without a user visible
interface other than the soc_device information. (yes, there
are a few historic counterexamples)

I also don't think this should be a hilicon specific interface,
if possible. The functionality is not that unusual in the end.

We had similar concepts using the numactl system calls in the
part, but I don't think we should do that here because you may
need the numa interfaces for other purposes as well, and it
may be confusing to existing callers.

Having a generic madvise() based interface would be great,
not sure if hardware support for that is common enough for that.

> +	/* Continuous physical memory is required for L3 cache lock. */
> +	pg = alloc_contig_pages(1 << order, GFP_KERNEL | __GFP_NOWARN | 
> __GFP_ZERO,
> +				cpu_to_node(smp_processor_id()), NULL);

Since this is a user allocation, should that be GFP_USER instead
of GFP_KERNEL?

> +/* HISI_L3C_INFO: cache lock info for HiSilicon SoC */
> +#define HISI_L3C_LOCK_INFO	_IOW(0xBB, 1, unsigned long)

The specification here looks wrong, please see
Documentation/driver-api/ioctl.rst

I think for your implementation it should be

#define HISI_L3C_LOCK_INFO	_IOR(0xBB, 1, hisi_l3c_lock_info)

> +struct hisi_l3c_lock_info {
> +	__u32 lock_region_num;
> +	__u64 lock_size;
> +	__u8 address_alignment;
> +	__u64 max_lock_size;
> +	__u64 min_lock_size;
> +};

You are leaking kernel data because of the padding in this structure,
please rearrange the members to avoid padding.

It may be better to use a different interface instead of ioctl(),
possibly exporting global data in sysfs.

       Arnd

  reply	other threads:[~2026-02-03 17:19 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-03 16:18 [PATCH 0/3] soc: Enable cache lockdown for HiSilicon L3 cache Yushan Wang
2026-02-03 16:18 ` [PATCH 1/3] soc cache: L3 cache driver for HiSilicon SoC Yushan Wang
2026-02-03 17:19   ` Arnd Bergmann [this message]
2026-02-04  9:51     ` wangyushan
2026-02-05  9:37     ` Krzysztof Kozlowski
2026-02-05 11:19       ` wangyushan
2026-02-05 11:23         ` Krzysztof Kozlowski
2026-02-05 11:30           ` wangyushan
2026-02-04  0:10   ` Linus Walleij
2026-02-04  9:53     ` wangyushan
2026-02-04 10:06       ` Linus Walleij
2026-02-04 13:40     ` Jonathan Cameron
2026-02-04 13:44       ` Jonathan Cameron
2026-02-05  2:20         ` SeongJae Park
2026-02-05  9:12       ` Linus Walleij
2026-02-05 10:18         ` Jonathan Cameron
2026-02-05 13:47           ` Linus Walleij
2026-02-05 14:38             ` Arnd Bergmann
2026-02-06  8:05               ` Linus Walleij
2026-02-05 14:37           ` Ben Horgan
2026-02-06  9:54           ` wangyushan
2026-02-06 16:15             ` Ben Horgan
2026-02-06 10:07       ` wangyushan
2026-02-06 10:44         ` Arnd Bergmann
2026-02-06 12:44         ` Linus Walleij
2026-02-04  2:47   ` kernel test robot
2026-02-03 16:18 ` [PATCH 2/3] soc cache: L3 cache lockdown support " Yushan Wang
2026-02-03 16:18 ` [PATCH 3/3] Documentation: soc cache: Add documentation to HiSilicon SoC cache Yushan Wang

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