* [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0
2024-05-13 11:44 [PATCH v2 0/3] arm64: dts: ti: Add USB support for J722S EVM Ravi Gunasekaran
@ 2024-05-13 11:44 ` Ravi Gunasekaran
2024-05-13 11:49 ` Ravi Gunasekaran
2024-05-13 11:44 ` [PATCH v2 2/3] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description Ravi Gunasekaran
2024-05-13 11:44 ` [PATCH v2 3/3] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 Ravi Gunasekaran
2 siblings, 1 reply; 6+ messages in thread
From: Ravi Gunasekaran @ 2024-05-13 11:44 UTC (permalink / raw)
To: nm, vigneshr, afd, robh, rogerq
Cc: kristo, krzk+dt, conor+dt, srk, r-gunasekaran, s-vadapalli,
linux-arm-kernel, devicetree, linux-kernel
AM62P's DT source files are reused for J722S inorder to
avoid duplication of nodes. But J722S has additional
peripherals that are not present in AM62P.
Introduce a -main.dtsi to define such additional main
domain peripherals and define the SERDES0 node.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
Changes since v1:
----------------
* Newly introduced k3-j722s-main.dtsi to add main domain
peripherals that are additionally present in J722S
* Used generic node names - renamed "clock-cmnrefclk" to "clk-0",
"wiz@f000000" to "phy@f000000"
v1: https://lore.kernel.org/all/20240429120932.11456-1-r-gunasekaran@ti.com/
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 64 +++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
new file mode 100644
index 000000000000..1fd88cc8545f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S main domain peripherals
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clk-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+};
+
+&cbass_main {
+ serdes_wiz0: phy@f000000 {
+ compatible = "ti,am64-wiz-10g";
+ ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <1>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+
+ assigned-clocks = <&k3_clks 279 1>;
+ assigned-clock-parents = <&k3_clks 279 5>;
+
+ serdes0: serdes@f000000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x0f000000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 279 1>,
+ <&k3_clks 279 1>,
+ <&k3_clks 279 1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled"; /* Needs lane config */
+ };
+ };
+};
+
+&main_conf {
+ serdes0_ln_ctrl: mux-controller@4080 {
+ compatible = "reg-mux";
+ reg = <0x4080 0x4>;
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x3>; /* SERDES0 lane0 select */
+ };
+};
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0
2024-05-13 11:44 ` [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0 Ravi Gunasekaran
@ 2024-05-13 11:49 ` Ravi Gunasekaran
0 siblings, 0 replies; 6+ messages in thread
From: Ravi Gunasekaran @ 2024-05-13 11:49 UTC (permalink / raw)
To: nm, vigneshr, afd, robh, rogerq
Cc: kristo, krzk+dt, conor+dt, srk, s-vadapalli, linux-arm-kernel,
devicetree, linux-kernel, Ravi Gunasekaran
Roger,
On 5/13/24 5:14 PM, Ravi Gunasekaran wrote:
> AM62P's DT source files are reused for J722S inorder to
> avoid duplication of nodes. But J722S has additional
> peripherals that are not present in AM62P.
>
> Introduce a -main.dtsi to define such additional main
> domain peripherals and define the SERDES0 node.
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> ---
> Changes since v1:
> ----------------
> * Newly introduced k3-j722s-main.dtsi to add main domain
> peripherals that are additionally present in J722S
>
> * Used generic node names - renamed "clock-cmnrefclk" to "clk-0",
> "wiz@f000000" to "phy@f000000"
>
[...]
> +
> +&cbass_main {
> + serdes_wiz0: phy@f000000 {
> + compatible = "ti,am64-wiz-10g";
> + ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <1>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> +
> + assigned-clocks = <&k3_clks 279 1>;
> + assigned-clock-parents = <&k3_clks 279 5>;
> +
> + serdes0: serdes@f000000 {
[1] expects the node name to be "serdes". So I could not rename this node to "phy"
as discussed in the v1 series.
[1] - https://elixir.bootlin.com/linux/latest/source/drivers/phy/ti/phy-j721e-wiz.c#L1474
> + compatible = "ti,j721e-serdes-10g";
[...]
--
Regards,
Ravi
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description
2024-05-13 11:44 [PATCH v2 0/3] arm64: dts: ti: Add USB support for J722S EVM Ravi Gunasekaran
2024-05-13 11:44 ` [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0 Ravi Gunasekaran
@ 2024-05-13 11:44 ` Ravi Gunasekaran
2024-05-13 11:44 ` [PATCH v2 3/3] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 Ravi Gunasekaran
2 siblings, 0 replies; 6+ messages in thread
From: Ravi Gunasekaran @ 2024-05-13 11:44 UTC (permalink / raw)
To: nm, vigneshr, afd, robh, rogerq
Cc: kristo, krzk+dt, conor+dt, srk, r-gunasekaran, s-vadapalli,
linux-arm-kernel, devicetree, linux-kernel
USB1 controller on J722S and AM62P are from different vendors.
Redefine the USB1 node description for J722S by deleting the
node inherited from AM62P dtsi.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
Changes since v1:
----------------
* The entire node which was added in k3-j722s.dtsi in v1 in now moved
to k3-j722s-main.dtsi as USB is a main domain peripheral
* Used generic node names - renamed "cdns-usb@f920000" to "usb@f920000"
v1: https://lore.kernel.org/all/20240429120932.11456-1-r-gunasekaran@ti.com/
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 39 +++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 1fd88cc8545f..54f37aff0eca 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -6,6 +6,13 @@
#include <dt-bindings/phy/phy-ti.h>
+/*
+ * USB1 controller on AM62P and J722S are of different IP.
+ * Delete AM62P's USBSS1 node definition and redefine it for J722S.
+ */
+
+/delete-node/ &usbss1;
+
/ {
serdes_refclk: clk-0 {
compatible = "fixed-clock";
@@ -52,6 +59,38 @@
status = "disabled"; /* Needs lane config */
};
};
+
+ usbss1: usb@f920000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x0f920000 0x00 0x100>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb1: usb@31200000{
+ compatible = "cdns,usb3";
+ reg = <0x00 0x31200000 0x00 0x10000>,
+ <0x00 0x31210000 0x00 0x10000>,
+ <0x00 0x31220000 0x00 0x10000>;
+ reg-names = "otg",
+ "xhci",
+ "dev";
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
};
&main_conf {
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 3/3] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1
2024-05-13 11:44 [PATCH v2 0/3] arm64: dts: ti: Add USB support for J722S EVM Ravi Gunasekaran
2024-05-13 11:44 ` [PATCH v2 1/3] arm64: dts: ti: k3-j722s-main: Add support for SERDES0 Ravi Gunasekaran
2024-05-13 11:44 ` [PATCH v2 2/3] arm64: dts: ti: k3-j722s-main: Redefine USB1 node description Ravi Gunasekaran
@ 2024-05-13 11:44 ` Ravi Gunasekaran
2024-05-24 5:44 ` Siddharth Vadapalli
2 siblings, 1 reply; 6+ messages in thread
From: Ravi Gunasekaran @ 2024-05-13 11:44 UTC (permalink / raw)
To: nm, vigneshr, afd, robh, rogerq
Cc: kristo, krzk+dt, conor+dt, srk, r-gunasekaran, s-vadapalli,
linux-arm-kernel, devicetree, linux-kernel
The GPIO expander on the EVM allows the USB selection for Type-C
port to either USB0 or USB1 via USB hub. By default, let the Type-C
port select USB0 via the GPIO expander port P05.
Enable super-speed on USB1 by updating SerDes0 lane configuration.
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
---
Changes since v1:
----------------
* Removed USB aliases, line-name property for p05 GPIO hog
* Included k3-j722s-main.dtsi
v1: https://lore.kernel.org/all/20240429120932.11456-1-r-gunasekaran@ti.com/
arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 55 +++++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j722s.dtsi | 5 +++
arch/arm64/boot/dts/ti/k3-serdes.h | 7 ++++
3 files changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1..531912be97c9 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
/dts-v1/;
#include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
#include "k3-j722s.dtsi"
+#include "k3-serdes.h"
/ {
compatible = "ti,j722s-evm", "ti,j722s";
@@ -202,6 +204,12 @@
J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
>;
};
+
+ main_usb1_pins_default: main-usb1-default-pins {
+ pinctrl-single,pins = <
+ J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+ >;
+ };
};
&cpsw3g {
@@ -301,6 +309,13 @@
"PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
"ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
"PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+ p05-hog {
+ /* P05 - USB2.0_MUX_SEL */
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ output-high;
+ };
};
};
@@ -384,3 +399,43 @@
status = "okay";
bootph-all;
};
+
+&serdes0_ln_ctrl {
+ idle-states = <J722S_SERDES0_LANE0_USB>,
+ <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+ status = "okay";
+ serdes0_usb_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz0 1>;
+ };
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "otg";
+ usb-role-switch;
+};
+
+&usbss1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb1_pins_default>;
+ ti,vbus-divider;
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ phys = <&serdes0_usb_link>;
+ phy-names = "cdns3,usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c75744edb143..61b64fae1bf4 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -87,3 +87,8 @@
reg = <0x00 0x70000000 0x00 0x40000>;
ranges = <0x00 0x00 0x70000000 0x40000>;
};
+
+/* Include bus peripherals that are additionally
+ * present in J722S
+ */
+ #include "k3-j722s-main.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index a011ad893b44..9082abeddcb1 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -201,4 +201,11 @@
#define J784S4_SERDES4_LANE3_USB 0x2
#define J784S4_SERDES4_LANE3_IP4_UNUSED 0x3
+/* J722S */
+#define J722S_SERDES0_LANE0_USB 0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2 0x1
+
+#define J722S_SERDES1_LANE0_PCIE0_LANE0 0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1 0x1
+
#endif /* DTS_ARM64_TI_K3_SERDES_H */
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 3/3] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1
2024-05-13 11:44 ` [PATCH v2 3/3] arm64: dts: ti: k3-j722s-evm: Update USB0 and USB1 Ravi Gunasekaran
@ 2024-05-24 5:44 ` Siddharth Vadapalli
0 siblings, 0 replies; 6+ messages in thread
From: Siddharth Vadapalli @ 2024-05-24 5:44 UTC (permalink / raw)
To: Ravi Gunasekaran
Cc: nm, vigneshr, afd, robh, rogerq, kristo, krzk+dt, conor+dt, srk,
s-vadapalli, linux-arm-kernel, devicetree, linux-kernel
On Mon, May 13, 2024 at 05:14:43PM +0530, Ravi Gunasekaran wrote:
> The GPIO expander on the EVM allows the USB selection for Type-C
> port to either USB0 or USB1 via USB hub. By default, let the Type-C
> port select USB0 via the GPIO expander port P05.
>
> Enable super-speed on USB1 by updating SerDes0 lane configuration.
>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> ---
>
[...]
> @@ -384,3 +399,43 @@
> status = "okay";
> bootph-all;
> };
> +
> +&serdes0_ln_ctrl {
> + idle-states = <J722S_SERDES0_LANE0_USB>,
> + <J722S_SERDES1_LANE0_PCIE0_LANE0>;
Patch 1/3 only added the Mux for Serdes0. So the idle-states property
for Serdes1 is incorrect and should be dropped.
[...]
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 6+ messages in thread