From: Guenter Roeck <linux@roeck-us.net>
To: Matthew Bettencourt <matthew.bettencourt@gmail.com>
Cc: linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [BUG] SPD5118 Intermittent MR11 Corruption During Suspend/Resume
Date: Tue, 1 Sep 2026 20:19:14 -0700 [thread overview]
Message-ID: <a953dcaa-cfff-40c8-85a9-c12601e49e85@roeck-us.net> (raw)
In-Reply-To: <65336f12-b821-449b-a637-31972807c676@gmail.com>
Hi Matthew,
On 9/1/26 19:14, Matthew Bettencourt wrote:
> Hello Guetner,
>
> I believe I implemented the print port correctly, below is the dmesg and piix4_sb800_port_sel() function.
>
> > Another idea might be to decode the ACPI data and see if there is anything
> > in there which accesses the SMBus controller.
>
> I have no problem grabbing the ACPI data or whatever is needed, just might need a little bit of guidance on that front. I am OK at c code with some AI help but never really delved into ACPI.
>
It would be something like
sudo acpidump > acpi.log
acpixtract acpi.log
iasl -d *.dat
You'll get a number of.dsl files with cryptic assembler-style
code and data. Then the digging starts ... you may find something
like "Name (SMB0, 0x0B00)" in dsdt.dsl. Then we can only hope to
figure out if ACPI actually accesses it.
> And one last thing I greatly appreciate all the time and effort you are putting into this. I would definitely not have been able to get this far without your help.
>
My pleasure.
> --- CMD=0b
> [19462.122064] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.123074] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.123109] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.124081] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.124115] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.125067] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.125074] [ T21668] spd5118 12-0053: PRE BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
> [19462.125094] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.126064] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.126072] [ T21683] spd5118 12-0051: PRE BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
> [19462.126088] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.127545] [ T21668] i2c i2c-12: [PIIX4 ERROR TRACE TRIGGERED] result=0
> STEP 1 (PRE-START) : CNT=08, CMD=0b, ADD=a7, DAT0=00, DAT1=18
> STEP 2 (START BIT SET): CNT=08, CMD=0b, ADD=a7, DAT0=00, DAT1=18
> STEP 3 (POST-WAIT) : STS=00, CNT=08, CMD=01, ADD=45, DAT0=ff, DAT1=18
> STEP 4 (POST-CLEANUP) : CNT=08, CMD=01, ADD=45, DAT0=ff, DAT1=18
Now we'll need to know the port number here (or even better at each step),
so some duplication of piix4_sb800_port_sel() which only reads the port
number will be needed.
Note that this may not help at all - whatever entity is modifying the registers
may not change the port number.
Thanks,
Guenter
> [19462.127556] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.127582] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.128217] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.128240] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.128894] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.128920] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.129561] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.129588] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.130227] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.130255] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.130894] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.130919] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.131560] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.131584] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.132226] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.132249] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.132882] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.132904] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.133555] [ T21683] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.133563] [ T21683] spd5118 12-0051: POST BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
> [19462.133581] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.134238] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19462.134244] [ T21668] spd5118 12-0053: POST BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x08
>
> --- CMD=1a
> [19664.445821] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.446491] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.446531] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.447201] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.447235] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.447890] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.447903] [ T21712] spd5118 12-0053: PRE BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
> [19664.447923] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.448574] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.448581] [ T21668] spd5118 12-0051: PRE BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
> [19664.448601] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.449239] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.449264] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.449886] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.449910] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.451402] [ T21712] i2c i2c-12: [PIIX4 ERROR TRACE TRIGGERED] result=0
> STEP 1 (PRE-START) : CNT=08, CMD=1a, ADD=a7, DAT0=00, DAT1=18
> STEP 2 (START BIT SET): CNT=08, CMD=1a, ADD=a7, DAT0=00, DAT1=18
> STEP 3 (POST-WAIT) : STS=00, CNT=08, CMD=01, ADD=45, DAT0=ff, DAT1=18
> STEP 4 (POST-CLEANUP) : CNT=08, CMD=01, ADD=45, DAT0=ff, DAT1=18
> [19664.451414] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.451438] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.452398] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.452423] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.453393] [ T21712] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.453400] [ T21712] spd5118 12-0053: POST BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
> [19664.453417] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.454396] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.454417] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.454883] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.454904] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.455541] [ T21668] piix4_smbus: PORT SEL -> requested=0x00 | hardware_was=0x00 | writing=0x07
> [19664.455549] [ T21668] spd5118 12-0051: POST BIT UPDATE: SUSPEND MR11 (0x0B) -> Cache: 0x00 | Bus: 0x00
>
>
> ---
> int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg)
> {
> u8 smba_en_lo, val, prev_port;
>
> if (mmio_cfg->use_mmio) {
> smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800);
> val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
> if (smba_en_lo != val)
> iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800);
>
> prev_port = smba_en_lo & piix4_port_mask_sb800;
> } else {
> outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
> smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
>
> val = (smba_en_lo & ~piix4_port_mask_sb800) | port;
> if (smba_en_lo != val)
> outb_p(val, SB800_PIIX4_SMB_IDX + 1);
>
> prev_port = smba_en_lo & piix4_port_mask_sb800;
> }
>
> /* Always print port state on every function call */
> pr_info("piix4_smbus: PORT SEL -> requested=0x%02x | hardware_was=0x%02x | writing=0x%02x\n",
> port, prev_port, val);
>
> return prev_port;
> }
>
>
> Thanks,
> Matthew
> On 9/1/26 8:32 PM, Guenter Roeck wrote:
>> On 9/1/26 17:57, Matthew Bettencourt wrote:
>>> Hello Guenter,
>>>
>>> These are the only boot up messages I see for SMBus/i2c/piix4
>>>
>>> [ 1.848113] [ T272] i2c_dev: i2c /dev entries driver
>>> [ 6.093885] [ T727] piix4_smbus 0000:00:14.0: SMBus Host Controller at 0xb00, revision 0
>>> [ 6.093888] [ T727] piix4_smbus 0000:00:14.0: Using register 0x02 for SMBus port selection
>>
>> So bus 12 and 13 share the same controller address.
>>
>> There is one more thing we can try: Print the selected port before and after
>> the access. The code to access the port number is in piix4_sb800_port_sel().
>> If we are "lucky", we may find that the selected port changed.
>>
>> Unfortunately that isn't going to help much since we'd still have
>> to figure out where that happens.
>>
>> Another idea might be to decode the ACPI data and see if there is anything
>> in there which accesses the SMBus controller.
>>
>> Thanks,
>> Guenter
>>
>>> [ 6.095020] [ T727] i2c i2c-12: Successfully instantiated SPD at 0x51
>>> [ 6.095981] [ T727] i2c i2c-12: Successfully instantiated SPD at 0x53
>>> [ 6.096039] [ T727] piix4_smbus 0000:00:14.0: Auxiliary SMBus Host Controller at 0xb20
>>>
>>>
>>> I don't see anything on bus 13 or 14, I added 10-12 as well for good measure.
>>> # sudo i2cdetect -y -a 14
>>> 0 1 2 3 4 5 6 7 8 9 a b c d e f
>>> 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> # sudo i2cdetect -y -a 13
>>> 0 1 2 3 4 5 6 7 8 9 a b c d e f
>>> 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> # sudo i2cdetect -y -a 12
>>> 0 1 2 3 4 5 6 7 8 9 a b c d e f
>>> 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 10: -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- --
>>> 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 40: -- -- -- -- -- -- -- -- -- 49 -- 4b -- -- -- --
>>> 50: -- 51 -- 53 -- -- -- -- -- -- -- -- -- -- -- --
>>> 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 70: -- 71 -- 73 -- -- -- -- -- -- -- -- -- -- 7e --
>>> # sudo i2cdetect -y -a 11
>>> 0 1 2 3 4 5 6 7 8 9 a b c d e f
>>> 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 30: 30 -- -- -- -- -- -- 37 -- -- -- -- -- -- -- --
>>> 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 50: 50 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> # sudo i2cdetect -y -a 10
>>> 0 1 2 3 4 5 6 7 8 9 a b c d e f
>>> 00: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 10: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 20: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 30: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 40: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 60: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>> 70: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
>>>
>>>
>>>
>>>
>
next prev parent reply other threads:[~2026-09-02 3:19 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-30 23:21 Matthew Bettencourt
2026-08-31 15:12 ` Guenter Roeck
2026-08-31 17:28 ` Guenter Roeck
2026-08-31 23:36 ` Matthew Bettencourt
[not found] ` <37132c40-aa82-4df1-b5ce-337601f3c085@gmail.com>
[not found] ` <3c4e9f59-5272-48cf-a4a0-eeefcba955a9@roeck-us.net>
2026-09-01 0:16 ` Matthew Bettencourt
2026-09-01 3:10 ` Guenter Roeck
2026-09-01 16:31 ` Matthew Bettencourt
2026-09-01 17:04 ` Guenter Roeck
2026-09-01 20:53 ` Matthew Bettencourt
2026-09-01 22:36 ` Guenter Roeck
2026-09-02 0:57 ` Matthew Bettencourt
2026-09-02 1:32 ` Guenter Roeck
2026-09-02 2:14 ` Matthew Bettencourt
2026-09-02 3:19 ` Guenter Roeck [this message]
2026-09-02 14:00 ` Matthew Bettencourt
2026-09-02 14:52 ` Guenter Roeck
2026-09-02 15:26 ` Matthew Bettencourt
2026-09-02 17:21 ` Guenter Roeck
2026-09-02 17:37 ` Matthew Bettencourt
2026-09-02 16:57 ` Armin Wolf
2026-09-02 17:08 ` Matthew Bettencourt
2026-09-02 17:22 ` Armin Wolf
2026-09-02 17:28 ` Matthew Bettencourt
2026-09-02 19:19 ` Armin Wolf
2026-09-02 19:25 ` Matthew Bettencourt
2026-09-02 19:31 ` Armin Wolf
2026-09-02 19:40 ` Matthew Bettencourt
2026-09-02 19:51 ` Armin Wolf
2026-09-03 18:01 ` Matthew Bettencourt
2026-09-03 18:16 ` Guenter Roeck
2026-09-03 18:25 ` Matthew Bettencourt
2026-09-03 21:05 ` Guenter Roeck
2026-09-03 22:47 ` Armin Wolf
2026-09-04 0:24 ` Matthew Bettencourt
2026-09-04 17:58 ` Guenter Roeck
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