From: Chao Gao <chao.gao@intel.com>
To: "Chang S. Bae" <chang.seok.bae@intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>,
Sean Christopherson <seanjc@google.com>, <x86@kernel.org>,
<linux-kernel@vger.kernel.org>, <kvm@vger.kernel.org>,
<tglx@linutronix.de>, <pbonzini@redhat.com>,
<peterz@infradead.org>, <rick.p.edgecombe@intel.com>,
<weijiang.yang@intel.com>, <john.allen@amd.com>, <bp@alien8.de>,
<xin3.li@intel.com>, Dave Hansen <dave.hansen@linux.intel.com>,
Eric Biggers <ebiggers@google.com>,
"H. Peter Anvin" <hpa@zytor.com>, Ingo Molnar <mingo@redhat.com>,
Kees Cook <kees@kernel.org>, Maxim Levitsky <mlevitsk@redhat.com>,
Mitchell Levy <levymitchell0@gmail.com>,
"Nikolay Borisov" <nik.borisov@suse.com>,
Oleg Nesterov <oleg@redhat.com>,
Sohil Mehta <sohil.mehta@intel.com>,
Stanislav Spassov <stanspas@amazon.de>,
"Vignesh Balasubramanian" <vigbalas@amd.com>
Subject: Re: [PATCH v8 0/6] Introduce CET supervisor state support
Date: Tue, 3 Jun 2025 14:22:11 +0800 [thread overview]
Message-ID: <aD6Ukwqz2Q5RKpEm@intel.com> (raw)
In-Reply-To: <434810d9-1b36-496d-a10d-41c6c068375e@intel.com>
On Mon, Jun 02, 2025 at 12:12:51PM -0700, Chang S. Bae wrote:
>== Preempt Case ==
>
>To illustrate how the XFD MSR state becomes incorrect in this scenario:
>
> task #1 (fpstate->xfd=0) task #2 (fpstate->xfd=0x80000)
> ======================== ==============================
> handle_signal()
> -> setup_rt_frame()
> -> get_siframe()
> -> copy_fpstate_to_sigframe()
> -> fpregs_unlock()
> ...
> ...
> switch_fpu_return()
> -> fpregs_restore_userregs()
> -> restore_fpregs_from_fpstate()
> -> xfd_write_state()
> ^ IA32_XFD_MSR = 0
> ...
> ...
> -> fpu__clear_user_states()
> -> fpregs_lock()
> -> restore_fpregs_from_init_fpstate()
> -> os_rstor()
> -> xfd_validate_state()
> ^ IA32_XFD_MSR != fpstate->xfd
> -> fpregs_mark_active()
> -> fpregs_unlock()
>
>Since fpu__clear_user_states() marks the FPU state as valid in the end, an
>XFD MSR sync-up was clearly missing.
Thanks for this analysis. It makes sense.
>
>== Return-to-Userspace Path ==
>
>Both tasks at that moment are on the return-to-userspace path, but at
>different points in IRQ state:
>
> * task #2 is inside handle_signal() and already re-enabled IRQs.
> * task #1 is after IRQ is disabled again when calling
> switch_fpu_return().
>
> local_irq_disable_exit_to_user()
> exit_to_user_mode_prepare()
> -> exit_to_user_mode_loop()
> -> local_irq_enable_exit_to_user()
> -> arch_do_signal_or_restart()
> -> handle_signal()
> -> local_irq_disable_exit_to_user()
> -> arch_exit_user_mode_prepare()
> -> arch_exit_work()
> -> switch_fpu_return()
>
>This implies that fpregs_lock()/fpregs_unlock() is necessary inside
>handle_signal() when XSAVE instructions are invoked.
>
>But, it should be okay for switch_fpu_return() to call
>fpregs_restore_userregs() without fpregs_lock().
>
>== XFD Sanity Checker ==
>
>The XFD sanity checker -- xfd_op_valid() -- correctly caught this issue in
>the test case. However, it may have a false negative when AMX usage was
>flipped between the two tasks.
>
>Despite that, I don't think extending its coverage is worthwhile, as it would
>complicate the logic. The current logic and documentation seem sound.
>
>== Fix Consideration ==
>
>I think the fix is straightforward: resynchronize the IA32_XFD MSR in
>fpu__clear_user_states().
This fix sounds good.
Btw, what do you think the impact of this issue might be?
Aside from the splat, task #2 could execute AMX instructions without
requesting permissions, but its AMX state would be discarded during the
next FPU switch, as RFBM[18] is cleared when executing XSAVES. And, in the
"flipped" scenario you mentioned, task #2 might receive an extra #NM, after
which its fpstate would be re-allocated (although the size won't increase
further).
So, for well-behaved tasks that never use AMX, there is no impact; tasks
that use AMX may receive extra #NM. There won't be any unexpected #PF,
memory corruption, or kernel panic.
next prev parent reply other threads:[~2025-06-03 6:22 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-22 15:10 Chao Gao
2025-05-22 15:10 ` [PATCH v8 1/6] x86/fpu/xstate: Differentiate default features for host and guest FPUs Chao Gao
2025-05-29 20:59 ` John Allen
2025-05-22 15:10 ` [PATCH v8 2/6] x86/fpu: Initialize guest FPU permissions from guest defaults Chao Gao
2025-05-29 21:14 ` John Allen
2025-05-22 15:10 ` [PATCH v8 3/6] x86/fpu: Initialize guest fpstate and FPU pseudo container " Chao Gao
2025-05-29 21:25 ` John Allen
2025-05-22 15:10 ` [PATCH v8 4/6] x86/fpu: Remove xfd argument from __fpstate_reset() Chao Gao
2025-05-29 21:26 ` John Allen
2025-05-22 15:10 ` [PATCH v8 5/6] x86/fpu/xstate: Introduce "guest-only" supervisor xfeature set Chao Gao
2025-05-30 16:04 ` John Allen
2025-05-22 15:10 ` [PATCH v8 6/6] x86/fpu/xstate: Add CET supervisor xfeature support as a guest-only feature Chao Gao
2025-05-30 16:05 ` John Allen
2025-05-23 16:57 ` [PATCH v8 0/6] Introduce CET supervisor state support Sean Christopherson
2025-05-23 17:12 ` Dave Hansen
2025-05-23 17:48 ` Sean Christopherson
2025-05-27 11:01 ` Chao Gao
2025-06-02 19:12 ` Chang S. Bae
2025-06-03 6:22 ` Chao Gao [this message]
2025-06-03 18:32 ` Chang S. Bae
2025-06-04 0:56 ` Chao Gao
2025-06-04 18:45 ` Dave Hansen
2025-06-16 8:08 ` Chao Gao
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