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From: Sean Christopherson <seanjc@google.com>
To: "Xin Li (Intel)" <xin@zytor.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	tglx@linutronix.de,  mingo@redhat.com, bp@alien8.de,
	dave.hansen@linux.intel.com, x86@kernel.org,  hpa@zytor.com,
	pbonzini@redhat.com, peterz@infradead.org, brgerst@gmail.com,
	 tony.luck@intel.com, fenghuay@nvidia.com
Subject: Re: [PATCH v1 1/3] x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h>
Date: Fri, 13 Jun 2025 07:18:43 -0700	[thread overview]
Message-ID: <aEwzQ9vIcaZPtDsw@google.com> (raw)
In-Reply-To: <20250613070118.3694407-2-xin@zytor.com>

On Fri, Jun 13, 2025, Xin Li (Intel) wrote:
> Move DR7_RESET_VALUE to <uapi/asm/debugreg.h> to prepare to write DR7
> with DR7_RESET_VALUE at boot time.

Alternatively, what about dropping DR7_RESET_VALUE,  moving KVM's DR6 and DR7
#defines out of arch/x86/include/asm/kvm_host.h, and then using DR7_FIXED_1?

Arguably, that'd be an improvement for 2 of the 3 uses of DR7_RESET_VALUE in SEV
code:

	/* Early non-zero writes to DR7 are not supported */
	if (!data && (val & ~DR7_RESET_VALUE))
		return ES_UNSUPPORTED;

vs.

	/* Early non-zero writes to DR7 are not supported */
	if (!data && (val & ~DR7_FIXED_1))
		return ES_UNSUPPORTED;

And in vc_handle_dr7_read():

	if (data)
		*reg = data->dr7;
	else
		*reg = DR7_RESET_VALUE;

vs.

	if (data)
		*reg = data->dr7;
	else
		*reg = DR7_FIXED_1;

In both of those cases, it isn't the RESET value that's interesting, it's that
architecturally bit 10 is fixed to '1'.

I haven't looked at the kernel code, but I suspect DR6_ACTIVE_LOW, DR6_VOLATILE,
and/or DR6_FIXED_1 could also come in handy. 

  reply	other threads:[~2025-06-13 14:18 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-13  7:01 [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization Xin Li (Intel)
2025-06-13  7:01 ` [PATCH v1 1/3] x86/traps: Move DR7_RESET_VALUE to <uapi/asm/debugreg.h> Xin Li (Intel)
2025-06-13 14:18   ` Sean Christopherson [this message]
2025-06-13 17:58     ` Xin Li
2025-06-13 20:03       ` Sean Christopherson
2025-06-13 21:38         ` Xin Li
2025-06-13  7:01 ` [PATCH v1 2/3] x86/traps: Initialize DR7 by writing its architectural reset value Xin Li (Intel)
2025-06-13  7:15   ` Peter Zijlstra
2025-06-13  7:51     ` Xin Li
2025-06-13  7:59       ` H. Peter Anvin
2025-06-13  8:16         ` Peter Zijlstra
2025-06-13 14:10     ` Sean Christopherson
2025-06-13 17:36       ` Xin Li
2025-06-13  7:01 ` [PATCH v1 3/3] x86/traps: Initialize DR6 " Xin Li (Intel)
2025-06-13  7:18 ` [PATCH v1 0/3] x86/traps: Fix DR6/DR7 inintialization Peter Zijlstra
2025-06-13  7:37   ` Xin Li
2025-06-13 22:43 ` Sohil Mehta
2025-06-13 23:22   ` Xin Li
2025-06-14  3:38     ` H. Peter Anvin
2025-06-16  8:15       ` Ethan Zhao

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