From: Frank Li <Frank.li@nxp.com>
To: Hans Zhang <18255117159@163.com>
Cc: lpieralisi@kernel.org, bhelgaas@google.com, mani@kernel.org,
kwilczynski@kernel.org, robh@kernel.org, jingoohan1@gmail.com,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 01/13] PCI: dwc: Add dw_pcie_clear_and_set_dword() for register bit manipulation
Date: Thu, 19 Jun 2025 00:29:22 -0400 [thread overview]
Message-ID: <aFOSIj1fimMwWCT7@lizhi-Precision-Tower-5810> (raw)
In-Reply-To: <20250618152112.1010147-2-18255117159@163.com>
On Wed, Jun 18, 2025 at 11:21:00PM +0800, Hans Zhang wrote:
> DesignWare PCIe controller drivers implement register bit manipulation
> through explicit read-modify-write sequences. These patterns appear
> repeatedly across multiple drivers with minor variations, creating
> code duplication and maintenance overhead.
>
> Implement dw_pcie_clear_and_set_dword() helper to encapsulate atomic
> register modification. The function reads the current register value,
> clears specified bits, sets new bits, and writes back the result in
> a single operation. This abstraction hides bitwise manipulation details
> while ensuring consistent behavior across all usage sites.
>
> Centralizing this logic reduces future maintenance effort when modifying
> register access patterns and minimizes the risk of implementation
> divergence between drivers.
>
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
> drivers/pci/controller/dwc/pcie-designware.h | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index ce9e18554e42..f401c144df0f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -707,6 +707,17 @@ static inline void dw_pcie_ep_writel_dbi2(struct dw_pcie_ep *ep, u8 func_no,
> dw_pcie_ep_write_dbi2(ep, func_no, reg, 0x4, val);
> }
>
> +static inline void dw_pcie_clear_and_set_dword(struct dw_pcie *pci, int pos,
> + u32 clear, u32 set)
Can align with regmap_update_bits() argumnet?
dw_pcie_update_dbi_bits()?
Frank
> +{
> + u32 val;
> +
> + val = dw_pcie_readl_dbi(pci, pos);
> + val &= ~clear;
> + val |= set;
> + dw_pcie_writel_dbi(pci, pos, val);
> +}
> +
> static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
> {
> u32 reg;
> --
> 2.25.1
>
next prev parent reply other threads:[~2025-06-19 4:29 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 15:20 [PATCH v2 00/13] PCI: dwc: Refactor register access with dw_pcie_clear_and_set_dword helper Hans Zhang
2025-06-18 15:21 ` [PATCH v2 01/13] PCI: dwc: Add dw_pcie_clear_and_set_dword() for register bit manipulation Hans Zhang
2025-06-19 4:29 ` Frank Li [this message]
2025-06-19 5:42 ` Hans Zhang
2025-06-19 15:12 ` Frank Li
2025-06-18 15:21 ` [PATCH v2 02/13] PCI: dwc: Refactor code by using dw_pcie_clear_and_set_dword() Hans Zhang
2025-06-18 15:21 ` [PATCH v2 03/13] PCI: dra7xx: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 04/13] PCI: imx6: " Hans Zhang
2025-06-19 15:16 ` Frank Li
2025-06-18 15:21 ` [PATCH v2 05/13] PCI: meson: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 06/13] PCI: armada8k: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 07/13] PCI: bt1: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 08/13] PCI: dw-rockchip: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 09/13] PCI: fu740: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 10/13] PCI: qcom: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 11/13] PCI: qcom-ep: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 12/13] PCI: rcar-gen4: " Hans Zhang
2025-06-18 15:21 ` [PATCH v2 13/13] PCI: tegra194: " Hans Zhang
2025-06-25 20:57 ` Manivannan Sadhasivam
2025-06-26 14:31 ` Hans Zhang
2025-06-25 21:00 ` [PATCH v2 00/13] PCI: dwc: Refactor register access with dw_pcie_clear_and_set_dword helper Manivannan Sadhasivam
2025-06-26 14:51 ` Hans Zhang
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