From: Alison Schofield <alison.schofield@intel.com>
To: Li Ming <ming.li@zohomail.com>
Cc: <akpm@linux-foundation.org>, <andriy.shevchenko@linux.intel.com>,
<bhelgaas@google.com>, <ilpo.jarvinen@linux.intel.com>,
<dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<dave.jiang@intel.com>, <vishal.l.verma@intel.com>,
<ira.weiny@intel.com>, <dan.j.williams@intel.com>,
<shiju.jose@huawei.com>, <linux-cxl@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/3] cxl/edac: Fix wrong dpa checking for PPR operation
Date: Wed, 2 Jul 2025 12:38:24 -0700 [thread overview]
Message-ID: <aGWKsBYX2kux7w9W@aschofie-mobl2.lan> (raw)
In-Reply-To: <20250702072008.468371-2-ming.li@zohomail.com>
On Wed, Jul 02, 2025 at 03:20:07PM +0800, Li Ming wrote:
> DPA 0 is considered invalid in cxl_do_ppr(), but per Table 8-143. "Get
> Partition Info Output Payload" in CXL r3.2 section 8.2.10.9.2.1 "Get
> Partition Info(Opcode 4100h)", it mentions that DPA 0 is a valid address
> of a CXL device. So the correct implementation should be checking if the
> DPA is in the DPA range of the CXL device rather than checking if the
> DPA is equal to 0.
>
> Fixes: be9b359e056a ("cxl/edac: Add CXL memory device soft PPR control feature")
> Signed-off-by: Li Ming <ming.li@zohomail.com>
> ---
> drivers/cxl/core/edac.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/core/edac.c b/drivers/cxl/core/edac.c
> index 623aaa4439c4..1cf65b1538b9 100644
> --- a/drivers/cxl/core/edac.c
> +++ b/drivers/cxl/core/edac.c
> @@ -1923,8 +1923,11 @@ static int cxl_ppr_set_nibble_mask(struct device *dev, void *drv_data,
> static int cxl_do_ppr(struct device *dev, void *drv_data, u32 val)
> {
> struct cxl_ppr_context *cxl_ppr_ctx = drv_data;
> + struct cxl_memdev *cxlmd = cxl_ppr_ctx->cxlmd;
> + struct cxl_dev_state *cxlds = cxlmd->cxlds;
>
> - if (!cxl_ppr_ctx->dpa || val != EDAC_DO_MEM_REPAIR)
> + if (!resource_contains_addr(&cxlds->dpa_res, cxl_ppr_ctx->dpa) ||
> + val != EDAC_DO_MEM_REPAIR)
> return -EINVAL;
Hi Ming,
I think this one needs a user visible impact statement.
I'm hoping the broader helper gets accepted. That may be the ioport.h
addition, or maybe we end up with a CXL special helper.
However, if this patch is aiming to go upstream as a FIX in a 6.16 rc,
then we are probably better off fixing the check inline right here, and
then you follow on with the other 2 patches to be considered for the
next merge window.
Please share that impact and suggest whether it can wait for next merge
window.
-- Alison
>
> return cxl_mem_perform_ppr(cxl_ppr_ctx);
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-07-02 19:39 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-02 7:20 [PATCH v2 1/3] resource: Introduce a new helper resource_contains_addr() Li Ming
2025-07-02 7:20 ` [PATCH v2 2/3] cxl/edac: Fix wrong dpa checking for PPR operation Li Ming
2025-07-02 8:24 ` Andy Shevchenko
2025-07-02 19:38 ` Alison Schofield [this message]
2025-07-03 9:57 ` Li Ming
2025-07-03 9:52 ` Shiju Jose
2025-07-02 7:20 ` [PATCH v2 3/3] cxl/core: Using resource_contains_addr() to check address availability Li Ming
2025-07-02 8:16 ` [PATCH v2 1/3] resource: Introduce a new helper resource_contains_addr() Andy Shevchenko
2025-07-02 8:18 ` Andy Shevchenko
2025-07-02 19:16 ` Alison Schofield
2025-07-03 9:31 ` Andy Shevchenko
2025-07-07 4:19 ` Li Ming
2025-07-02 8:21 ` Andy Shevchenko
2025-07-03 5:33 ` Li Ming
2025-07-03 9:52 ` Shiju Jose
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