From: Jorge Ramirez <jorge.ramirez@oss.qualcomm.com>
To: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Dikshita Agarwal <quic_dikshita@quicinc.com>,
Vikash Garodia <quic_vgarodia@quicinc.com>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] media: iris: vpu3x: Add MNoC low power handshake during hardware power-off
Date: Tue, 12 Aug 2025 11:24:24 +0200 [thread overview]
Message-ID: <aJsISDlgx1EZCzKn@trex> (raw)
In-Reply-To: <acdff7a4-bd9f-45c1-b620-25e667d1f628@linaro.org>
On 12/08/25 10:06:40, Neil Armstrong wrote:
> On 12/08/2025 09:48, Dikshita Agarwal wrote:
> > Add the missing write to AON_WRAPPER_MVP_NOC_LPI_CONTROL before
> > reading the LPI status register. Introduce a handshake loop to ensure
> > MNoC enters low power mode reliably during VPU3 hardware power-off with
> > timeout handling.
> >
> > Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
> > ---
> > drivers/media/platform/qcom/iris/iris_vpu3x.c | 23 +++++++++++++++++++++--
> > 1 file changed, 21 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> > index 9b7c9a1495ee2f51c60b1142b2ed4680ff798f0a..c2e6af575cbe4b3e3f2a019b24eecf3a5d469566 100644
> > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> > @@ -110,6 +110,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core)
> > static void iris_vpu33_power_off_hardware(struct iris_core *core)
> > {
> > u32 reg_val = 0, value, i;
> > + u32 count = 0;
> > int ret;
> > if (iris_vpu3x_hw_power_collapsed(core))
> > @@ -128,13 +129,31 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core)
> > goto disable_power;
> > }
> > + /* set MNoC to low power */
> > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
> > +
> > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
> > +
for readibility purposes, could this code be restructed a bit
differently? maybe all the write/read operations in a single do while
loop with the exit conditions assigned to variables with an
identifiable meaning?
maybe also check/report errors outside the loop itself?
> > + while (!(value & BIT(0)) && (value & BIT(2) || value & BIT(1))) {
> > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
> > +
> > + usleep_range(10, 20);
> > +
> > + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
> > +
> > + value = readl(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS);
> > + if (++count >= 1000) {
> > + dev_err(core->dev, "LPI handshake timeout\n");
> > + break;
> > + }
> > + }
> > +
> > ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS,
> > reg_val, reg_val & BIT(0), 200, 2000);
> > if (ret)
> > goto disable_power;
> > - /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */
> > - writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
> > + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL);
> > writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE,
> > core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET);
> >
> > ---
> > base-commit: d968e50b5c26642754492dea23cbd3592bde62d8
> > change-id: 20250812-sm8650-power-sequence-fix-ba9a92098233
> >
> > Best regards,
>
> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
>
> Thanks,
> Neil
>
next prev parent reply other threads:[~2025-08-12 9:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-12 7:48 Dikshita Agarwal
2025-08-12 8:06 ` Neil Armstrong
2025-08-12 9:24 ` Jorge Ramirez [this message]
2025-08-12 8:58 ` Konrad Dybcio
2025-08-12 9:00 ` Bryan O'Donoghue
2025-08-12 9:31 ` Dikshita Agarwal
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