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From: Nicolin Chen <nicolinc@nvidia.com>
To: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: <jgg@nvidia.com>, <linux-kernel@vger.kernel.org>,
	<robin.murphy@arm.com>, <will@kernel.org>, <joro@8bytes.org>,
	<kevin.tian@intel.com>, <jsnitsel@redhat.com>,
	<vasant.hegde@amd.com>, <iommu@lists.linux.dev>,
	<santosh.shukla@amd.com>, <sairaj.arunkodilkar@amd.com>,
	<jon.grimm@amd.com>, <prashanthpra@google.com>, <wvw@google.com>,
	<wnliu@google.com>, <gptran@google.com>, <kpsingh@google.com>,
	<joao.m.martins@oracle.com>, <alejandro.j.jimenez@oracle.com>
Subject: Re: [PATCH v5 11/14] iommu/amd: Introduce gDomID-to-hDomID Mapping and handle parent domain invalidation
Date: Thu, 13 Nov 2025 12:36:07 -0800	[thread overview]
Message-ID: <aRZBN/nBz6lqTzmt@Asurada-Nvidia> (raw)
In-Reply-To: <20251112182506.7165-12-suravee.suthikulpanit@amd.com>

On Wed, Nov 12, 2025 at 06:25:03PM +0000, Suravee Suthikulpanit wrote:
> @@ -38,10 +40,42 @@ size_t amd_iommufd_get_viommu_size(struct device *dev, enum iommu_viommu_type vi
>  int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain *parent,
>  			    const struct iommu_user_data *user_data)
>  {
> +	unsigned long flags;
>  	struct protection_domain *pdom = to_pdomain(parent);
>  	struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core);
>  
> +	xa_init(&aviommu->gdomid_array);

Perhaps init with XA_FLAGS_ALLOC1 since domid can't be 0?

> +static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu)
> +{
> +	unsigned long flags;
> +	struct amd_iommu_viommu *entry, *next;
> +	struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core);
> +	struct protection_domain *pdom = aviommu->parent;
> +
> +	spin_lock_irqsave(&pdom->lock, flags);
> +	list_for_each_entry_safe(entry, next, &pdom->viommu_list, pdom_list) {
> +		if (entry == aviommu)
> +			list_del(&entry->pdom_list);
> +	}

Do we really need the loop? Why not simply do list_del()?

> +	spin_unlock_irqrestore(&pdom->lock, flags);
> +
> +}

No need of the extra line at the end of the function.

> @@ -92,7 +94,60 @@ amd_iommu_alloc_domain_nested(struct iommufd_viommu *viommu, u32 flags,
>  	ndom->domain.type = IOMMU_DOMAIN_NESTED;
>  	ndom->viommu = aviommu;
>  
> +	gdom_info = kzalloc(sizeof(*gdom_info), GFP_KERNEL);
> +	if (!gdom_info)
> +		goto out_err;

Missing:
	ret = -ENOMEM;

> +
> +	/*
> +	 * Normally, when a guest has multiple pass-through devices,
> +	 * the IOMMU driver setup DTEs with the same stage-2 table and
> +	 * use the same host domain ID (hDomId). In case of nested translation,
> +	 * if the guest setup different stage-1 tables with same PASID,
> +	 * IOMMU would use the same TLB tag. This will results in TLB
> +	 * aliasing issue.
> +	 *
> +	 * The guest is assigning gDomIDs based on its own algorithm for managing
> +	 * cache tags of (DomID, PASID). Within a single viommu, the nest parent domain
> +	 * (w/ S2 table) is used by all DTEs. But we need to consistently map the gDomID
> +	 * to a single hDomID. This is done using an xarray in the vIOMMU to
> +	 * keep track of the gDomID mapping. When the S2 is changed, the INVALIDATE_IOMMU_PAGES
> +	 * command must be issued for each hDomID in the xarray.
> +	 */
> +	curr = xa_cmpxchg(&aviommu->gdomid_array,
> +			  ndom->gdom_id, NULL, gdom_info, GFP_ATOMIC);
> +	if (curr) {
> +		if (xa_err(curr)) {
> +			ret = -EINVAL;
> +			goto out_err_gdom_info;
> +		} else {
> +			/* The gDomID already exist */
> +			pr_debug("%s: Found gdom_id=%#x, hdom_id=%#x\n",
> +				 __func__, ndom->gdom_id, curr->hdom_id);
> +			refcount_inc(&curr->users);
> +			ndom->gdom_info = curr;

This looks racy..

When a gDomID is shared between two nested domains, a concurrent
nested_domain_free() could enter before refcount_inc(), and call
refcount_dec_and_test() or even free the curr and ndom.

Then, this refcount_inc() will blow up, or curr/ndom will UAF.

Actually, I don't see where amd_iommu_alloc_domain_nested() gets
used in this series.. I assume AMD will use the iommufd's vIOMMU
infrastructure directly which doesn't mutex across nested domain
allocation/free calls.

So, the entire thing here should hold xa_lock(), use xas_load()
for the existing curr and use xas_store() to store gdom_info if
!curr, and xa_unlock() after gdom_info is fully initialized.

> +			kfree(gdom_info);
> +			return &ndom->domain;
> +		}
> +	}
> +
> +	/* The gDomID does not exist. We allocate new hdom_id */
> +	gdom_info->hdom_id = amd_iommu_pdom_id_alloc();
> +	if (gdom_info->hdom_id <= 0) {
> +		xa_cmpxchg(&aviommu->gdomid_array,
> +			   ndom->gdom_id, gdom_info, NULL, GFP_ATOMIC);
> +		ret = -ENOSPC;
> +		goto out_err_gdom_info;
> +	}
> +
> +	refcount_set(&gdom_info->users, 1);

Similar risk here. gdom_info is stored to the xarray before this
line. A concurrent amd_iommu_alloc_domain_nested() could get the
stored gdom_info and blow up at refcount_inc().

Make sure the entire thing is locked and safe.

Nicolin

  reply	other threads:[~2025-11-13 20:36 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-12 18:24 [PATCH v5 00/14] iommu/amd: Introduce Nested Translation support Suravee Suthikulpanit
2025-11-12 18:24 ` [PATCH v5 01/14] iommu/amd: Rename DEV_DOMID_MASK to DTE_DOMID_MASK Suravee Suthikulpanit
2025-11-12 18:24 ` [PATCH v5 02/14] iommu/amd: Make amd_iommu_pdom_id_alloc() non-static Suravee Suthikulpanit
2025-11-12 18:24 ` [PATCH v5 03/14] iommu/amd: Make amd_iommu_pdom_id_free() non-static Suravee Suthikulpanit
2025-11-12 18:24 ` [PATCH v5 04/14] iommu/amd: Make amd_iommu_make_clear_dte() non-static inline Suravee Suthikulpanit
2025-11-18 23:44   ` Jason Gunthorpe
2025-11-12 18:24 ` [PATCH v5 05/14] iommu/amd: Introduce helper function amd_iommu_update_dte() Suravee Suthikulpanit
2025-11-13 19:18   ` Nicolin Chen
2026-01-15  9:20     ` Suthikulpanit, Suravee
2025-11-18 23:50   ` Jason Gunthorpe
2025-11-12 18:24 ` [PATCH v5 06/14] iommufd: Introduce data struct for AMD nested domain allocation Suravee Suthikulpanit
2025-11-12 18:24 ` [PATCH v5 07/14] iommu/amd: Always enable GCR3TRPMode when supported Suravee Suthikulpanit
2025-11-13 19:19   ` Nicolin Chen
2025-11-12 18:25 ` [PATCH v5 08/14] iommu/amd: Add support for nest parent domain allocation Suravee Suthikulpanit
2025-11-12 18:25 ` [PATCH v5 09/14] iommu/amd: Introduce struct amd_iommu_viommu Suravee Suthikulpanit
2025-11-13 19:21   ` Nicolin Chen
2025-11-12 18:25 ` [PATCH v5 10/14] iommu/amd: Add support for nested domain allocation Suravee Suthikulpanit
2025-11-12 18:25 ` [PATCH v5 11/14] iommu/amd: Introduce gDomID-to-hDomID Mapping and handle parent domain invalidation Suravee Suthikulpanit
2025-11-13 20:36   ` Nicolin Chen [this message]
2025-11-19  0:02     ` Jason Gunthorpe
2026-01-15  9:25       ` Suthikulpanit, Suravee
2026-01-15  9:21     ` Suthikulpanit, Suravee
2025-11-19  0:11   ` Jason Gunthorpe
2025-11-19  1:10     ` Nicolin Chen
2025-11-12 18:25 ` [PATCH v5 12/14] iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte() Suravee Suthikulpanit
2025-11-13 20:42   ` Nicolin Chen
2025-11-12 18:25 ` [PATCH v5 13/14] iommu/amd: Refactor logic to program the host page table in DTE Suravee Suthikulpanit
2025-11-13 21:19   ` Nicolin Chen
2025-11-13 21:29     ` Nicolin Chen
2025-11-19  0:21       ` Jason Gunthorpe
2025-11-19  0:20     ` Jason Gunthorpe
2026-01-15  9:24     ` Suthikulpanit, Suravee
2025-11-19  0:18   ` Jason Gunthorpe
2025-11-12 18:25 ` [PATCH v5 14/14] iommu/amd: Add support for nested domain attach/detach Suravee Suthikulpanit
2025-11-13 21:34   ` Nicolin Chen
2025-11-19  0:28   ` Jason Gunthorpe
2025-11-13 21:52 ` [PATCH v5 00/14] iommu/amd: Introduce Nested Translation support Nicolin Chen
2025-11-17 17:54   ` Jason Gunthorpe
2026-01-15  9:18     ` Suthikulpanit, Suravee

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